Z8018008VEC Zilog, Z8018008VEC Datasheet - Page 68
Z8018008VEC
Manufacturer Part Number
Z8018008VEC
Description
IC 8MHZ Z180 CMOS ENH MPU 68PLCC
Manufacturer
Zilog
Datasheet
1.Z8018006PSG.pdf
(85 pages)
Specifications of Z8018008VEC
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3012
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Quantity
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Part Number:
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DMA I/O Address Register Channel 1B
DMA Status Register (DSTAT: I/O Address = 30h)
PS014004-1106
DMA I/O Address Register Channel 1B
DMA Status Register (DSTAT)
Bit
Mnemonic IAR1B (Address 2D)
DSTAT
also indicates DMA transfer status, in other words, completed or in progress.
Mnemonic DSTAT (Address 30)
DE1: DMA Enable Channel 1 (bit 7)—When
enabled. When a DMA transfer terminates (
When
made to the CPU.
To perform a software
WRITE
DE1
DE1
DE0: DMA Enable Channel 0 (bit 6)—When
enabled. When a DMA transfer terminates (
R/W
DE1
to
is cleared to
7
Figure 65. DMA Status Register (DSTAT: I/O Address = 30h)
DE1 = 0
1
is used to enable and disable DMA transfer and DMA termination interrupts.
access. Writing
enables channel 1 DMA and automatically sets
Figure 64. DMA I/O Address Register Channel 1B
R/W
DE0
6
and the DMA interrupt is enabled (
0
during
—
DWE1
W
5
3
WRITE
DE1
—
RESET
2
DWE0
to
W
—
4
to
0
DMA I/O Channel B Address
DE1
disables channel 1 DMA, but DMA is restartable. Writing
1
.
—
DIE1
R/W
,
DWE1
3
0
BCR1 = 0
BCR0 = 0
DIE0
R/W
must be written with
2
DIE1 = 1
DE1 = 1
DE0 = 1
),
),
1
DE1
DE0
DME
and
), a DMA interrupt request is
and
is reset to
is reset to
DME
(DMA Main Enable) to
DME = 1
DME = 1
R
0
0
during the same register
Microprocessor Unit
0
0
, channel 1 DMA is
, channel 0 DMA is
by the DMAC.
by the DMAC.
Architecture
Z80180
DSTAT
1
.
62