EZ80190AZ050EC00TR Zilog, EZ80190AZ050EC00TR Datasheet - Page 15
EZ80190AZ050EC00TR
Manufacturer Part Number
EZ80190AZ050EC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device
PS006614-1208
Pin
No.
1
2
3
4
5
6
7
8
9
Symbol
MREQ
WR
RD
CS0
CS1
CS2
CS3
V
GND
DD
Function
Memory
Request
Write
Read
Chip Select 0
Chip Select 1
Chip Select 2
Chip Select 3
Power Supply
Ground
Signal Direction
Input/Output,
Active Low
Output, Active Low WR indicates the CPU is writing to the current
Output, Active Low RD indicates the eZ80190 device is reading from
Output, Active Low CS0 indicates access in the defined CS0 memory
Output, Active Low CS1 indicates access in the defined CS1 memory
Output, Active Low CS2 indicates access in the defined CS2 memory
Output, Active Low CS3 indicates access in the defined CS3 memory
Description
MREQ indicates the CPU is accessing a location
in memory. The RD, WR, and INSTRD signals
indicate the type of access. The eZ80190 device
does not drive this line during Reset. It is an input
in bus acknowledge cycles.
address location. The device accessed is
determined by the IORQ and MREQ pins. The
WR pin is tristated during bus acknowledge
cycles.
the current address location. This pin is tristated
during bus acknowledge cycles.
or I/O address space. This signal is still driven
during bus acknowledge cycles and is generated
from the address and control provided on the
external pins.
or I/O address space. This signal is still driven
during bus acknowledge cycles and is generated
from the address and control provided on the
external pins.
or I/O address space. This signal is still driven
during bus acknowledge cycles and is generated
from the address and control provided on the
external pins.
or I/O address space. This signal is still driven
during bus acknowledge cycles and is generated
from the address and control provided on the
external pins.
Power Supply
Ground
Product Specification
Architectural Overview
5
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