EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 85
EZ80190AZ050SC00TR
Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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PS006614-1208
UART Interrupt Identification Register
Table 29. UART Interrupt Identification Registers
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:6]
FSTS
[5:4]
[3:1]
INSTS
0
INTBIT
The Read Only UART Interrupt Identification register, listed in
check the status of interrupts and whether the FIFO is enabled. These registers share the
same I/O addresses as the UARTx_FCTL registers. Status codes for the UARTx_IIR reg-
ister are listed in
Table 30. UART Interrupt Status Codes
INSTS
Value
011
010
110
001
000
Value
00
11
00
000–
110
0
1
Table
Description
FIFO is disabled.
FIFO is enabled.
Reserved
Interrupt Status Code
The code indicated in these three bits is valid only if the
interrupt bit is 1. If two internal interrupt sources are active and
their respective enable bits are High, only the higher priority
interrupt is seen by the application. The lower priority interrupt
code is indicated only after the higher priority interrupt is
serviced.
There is an active interrupt source within the UART.
There is not an active interrupt source within the UART.
R
Priority
Highest
Second
Third
Fourth
Lowest
7
0
30.
R
6
0
Table 30
Interrupt Type
Receiver Line Status
Receive Data Ready or Trigger Level
Character Time-out
Transmit Buffer Empty
Modem Status
R
5
0
lists interrupt status codes.
R
4
0
(UART0_IIR = C2h, UART1_IIR = D2h)
Universal Asynchronous Receiver/Transmitter
R
3
0
R
2
0
Table
Product Specification
R
1
0
29, allows you to
R
0
1
eZ80190
75
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