Z84C9008VEG Zilog, Z84C9008VEG Datasheet - Page 21

• Manufacturer Part Number: Z84C9008VEG
• Description: IC 8MHZ Z80 KIO XTEMP 84-PLCC
• Manufacturer: Zilog

Specifications of Z84C9008VEG

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. AC Characteristics of the Z84C90 (Continued)
PS011802-0902
No. Symbol
22 TsIEI(Cf)
23 TsIOr(Cf)
PIO Timing
24 TdCf(RDYr)
25 TdCf(RDYf)
26 TwSTB
27 TsSTBr(Cf)
28 TdIOf(PD)
29 TsPD(STBr)
30 TdSTBI(PD)
31 TdSTBr(PDz)
32 TdPD(INTf)
33 TdSTBr(INTf)
34 TsPD(RIf)
35 TdCr(PD)
CTC Timing
36 TdCr(INTf)
37 TsCTRr(Cr)c
38 TsCTRr(Cr)t
CLK/TRG Rise to Clock Rise Setup
CLK/TRG Rise to Clock Rise Setup
Parameter
IEI to Clock Fall Setup (for 4D
Decode)
IORQ Rise to Clock Fall Setup
(to activate RDY on next clock)
Clock Fall to RDY Rise Delay
Clock Fall to RDY Fall Delay
STB Pulse Width
STB Rise to Clock Fall Setup
(to activate RDY on next clock
cycle)
IORQ Fall to Port Data Valid
(Mode 0)
Port A,B Data to STB Rise Setup
Time (Mode 1)
STB Fall to Port A,B Data Valid
Delay (Mode 2)
STB Rise to Port Data Float Delay
(Mode 2)
Port Data Match to INT Fall Delay
(Mode 3)
STB Rise to INT Fall Delay
PIA Port Data to RD, IORQ Fall
Setup
Clock Rise to Port Data Valid Delay
Clock Rise to INT Rise Delay
(for immediate count, Counter
mode)
(for enabling prescaler on following
Clock Rise, Timer mode)
TBD
Min
100
100
100
140
50
90
90
TcC+100
8MHz
KIO Serial/Parallel Counter Timer
Max
100
100
140
150
140
250
290
80
TBD
Min
100
100
40
80
75
90
90
10MHz
TcC+80
Max
100
100
120
120
120
200
220
80
1
Min Max U/M
30
12MHz
Z84C90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
ns
ns
ns
ns
16