GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 22

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
Errata
22
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IXP1200 Network Processor
}
; Filename: tands.uc
; test-and-set code for Microengines
#define TANDSBIT 0x01
#define COREBIT
#define CASE00 0
#define CASE01 TANDSBIT
#define CASE10 COREBIT
#define CASE11 (TANDSBIT | COREBIT)
start#:
take_sem#:
core_loop#:
immed[addr, 0]
immed[$xfer, TANDSBIT]
sram[bit_wr, $xfer, addr, 0, test_and_set_bits], ctx_swap
; case 00, got ownership
alu[--, $xfer, -, CASE00]
br=0[got_it#]
; case 01, another Microengine has ownership, try again
alu[--, $xfer, -, CASE01]
br=0[take_sem#]
; case 10, StrongARM* core has ownership
alu[--, $xfer, -, CASE10]
br!=0[core_loop#]
; need to clear 1
sram[bit_wr, $xfer, addr, 0, clear_bits]
; case 11 or 10, StrongARM* core has ownership
; loop until 0x
sram[read, $xfer, addr, 0, 1], ctx_swap
alu[--, $xfer, and~, TANDSBIT]
br!=0[core_loop#]
; try again
br[take_sem#]
}
return i + 0x10000;
/*
Place code here to access locked resource
*/
} /* end while 1 */
/* got test-and-set */
/* get data */
/* release test-and-set */
IXP1200_REG_WRITE(CLEAR_ADDR, COREBIT);
if (xfer == COREBIT)
if (xfer != (COREBIT | TANDSBIT)) {
}
taskDelay(1);
break;
printf("Error: word addr = %X\n",xfer);
return xfer;
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Specification Update