GCIXP1240AB Intel, GCIXP1240AB Datasheet - Page 22

• Manufacturer Part Number: GCIXP1240AB
• Description: IC MPU NETWORK 200MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AB

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837151

Intel
Specification Clarifications
Specification Clarifications
1.
Issue:
2.
Issue:
3.
Issue:
22
®
IXP1240 Network Processor
SRAM Unlocks and Write Unlocks
Documentation had indicated that performing an SRAM write_unlock on a memory location that
was not locked would only result in an SRAM write, and that an SRAM unlock on a memory
address that was not locked would result in no action. In actuality, unlocking an SRAM address
that is not locked will result in corruption of internal CAM pointer leading to unpredictable results.
The internal CAM pointer is implemented as a 4-bit counter which indicates the number of
outstanding locks that are present in the CAM. The unlock/write_unlock of an address that is not
present in the CAM will incorrectly decrement this counter. This could result in corruption of CAM
contents and failure of read_locks which should have been successful. Depending on the frequency
of incorrect unlocks write_unlocks, and the overall program flow, this could result in data
corruption, or eventual hang of one or more threads.
Maximum Number of Chain_Ref Instructions
Documentation has not adequately described that for SDRAM and SDRAM_CRC instructions, the
maximum number of instructions that may be chained together using the chain_ref optional token
is five. Chaining more than five instructions runs the risk of overflowing the SDRAM queues,
resulting in dropped references.
DMA Receive in Big Endian Mode
The documentation does not clearly describe the PCI receive operation when Big Endian Data In is
set. The fact that byte swapping occurs before the data is aligned was not clearly articulated. The
clarification in
Figure 2
will eliminate all ambiguities.
Specification Update