MPC8260AZUMHBB Freescale Semiconductor, MPC8260AZUMHBB Datasheet - Page 5

• Manufacturer Part Number: MPC8260AZUMHBB
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8260AZUMHBB

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 266MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Processor Series: MPC8xxx
• Core: 603e
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): No
• Rohs Compliant: No
• For Use With: MPC8260ADS-TCOM - BOARD DEV ADS POWERQUICC II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Additional features of the MPC826xA family are as follows:
Freescale Semiconductor
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MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I
— Up to eight TDM interfaces (four on the MPC8255)
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
CPM
— 32-Kbyte dual-port RAM
— Additional MCC host commands
— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
CPM multiplexing
— FCC2 can also be connected to the TC layer.
TC layer (MPC8264 and MPC8266 only)
— Each of the 8 TDM channels is routed in hardware to a TC layer block
– Transparent
– UART (low-speed operation)
– Microwire compatible
– Multiple-master, single-master, and slave modes
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
SCCs, SMCs, and serial channels
inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only)
– Protocol-specific overhead bits may be discarded or routed to other controllers by the SI
– Performing ATM TC layer functions (according to ITU-T I.432)
– Transmit (Tx) updates
– Receive (Rx) updates
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
- Cell HEC generation
- Payload scrambling using self synchronizing scrambler (programmable by the user)
- Coset generation (programmable by the user)
- Cell rate by inserting idle/unassigned cells
- Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
parameters for the delineation state machine
- Payload descrambling using self synchronizing scrambler (programmable by the user)
2
C) controller (identical to the MPC860 I
2
C controller)
Features
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