MPC866PZP133A Freescale Semiconductor, MPC866PZP133A Datasheet - Page 37

• Manufacturer Part Number: MPC866PZP133A
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICCr

Specifications of MPC866PZP133A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Core Size: 32 Bit
• Program Memory Size: 24KB
• Cpu Speed: 133MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Supply Voltage Range: 1.7V To 1.9V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 23
Figure 24
Table 10
Freescale Semiconductor
1
Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Num
I39
I40
I41
I42
I43
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has
no direct relation with the total system interrupt latency that the MPC866/859 is able to support.
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
shows the interrupt timing for the MPC866/859.
CSx, WE[0:3],
shows the timing for the asynchronous external master memory access controlled by the GPCM.
shows the timing for the asynchronous external master control signals negation.
TSIZ[0:1],
CLKOUT
OE, GPLx,
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
IRQx pulse width high
IRQx edge-to-edge time
A[0:31],
BS[0:3]
R/W
CSx
AS
Figure 24. Asynchronous External Master—Control Signals Negation Timing
AS
MPC866/MPC859 Hardware Specifications, Rev. 2
Characteristic
Table 10. Interrupt Timing
B40
B39
1
B43
4xT
B22
All Frequencies
CLOCKOUT
2.00
3.00
3.00
6.00
Min
Bus Signal Timing
Max
—
—
—
—
—
Unit
ns
ns
ns
ns
—
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