MPC8245TVV333D Freescale Semiconductor, MPC8245TVV333D Datasheet - Page 15

• Manufacturer Part Number: MPC8245TVV333D
• Description: IC MPU 32BIT 333MHZ PPC 352-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8245TVV333D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 333MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Processor Series: MPC8xxx
• Core: 603e
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 2 V, 2.1 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 6
Table
Figure 7
graphs define the areas of DLL locking for various modes. The gray areas show where the DLL locks.
Freescale Semiconductor
At recommended operating conditions (see
Notes:
1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable
6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see
7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are
Num
16
17
19
20
21
added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance
between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew between
SDRAM_CLKs can be measured, the relationship between the internal sys_logic_clk and the external SDRAM_SYNC_IN
cannot be measured and is guaranteed by design.
V
disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
of one SDRAM_SYNC_OUT clock cycle in ns. T
board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner)
corresponds to approximately 1 ns of delay. For details about how
Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for details on MPC8245
memory clock design.
not tested.
DD
8.
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been
DLL lock range for other modes
Frequency of operation (OSC_IN)
OSC_IN rise and fall times
OSC_IN duty cycle measured at 1.4 V
OSC_IN frequency stability
shows the PCI_SYNC_IN input clock timing diagram with the labeled number items listed in
through
PCI_SYNC_IN
Figure 10
Characteristics and Conditions
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Table 8. Clock AC Timing Specifications (continued)
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
show the DLL locking range loop delay vs. frequency of operation. These
VM
Table
5a
2) with LV
VM = Midpoint Voltage (1.4 V)
1
VM
loop
DD
5b
is the propagation delay of the DLL synchronization feedback loop (PC
= 3.3 V ± 0.3 V
VM
Figure 7
See
Figure 8
Min
25
40
—
—
through
Figure 7
2
through
Figure 10
through
Electrical and Thermal Characteristics
Figure 10
Max
100
66
60
5
may be used refer to the
Figure
10). T
MHz
Unit
ppm
3
ns
ns
%
clk
is the period
Notes
6
7
15