MPC852TCVR50A Freescale Semiconductor, MPC852TCVR50A Datasheet - Page 68
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MPC852TCVR50A
Manufacturer Part Number
MPC852TCVR50A
Description
IC MPU POWERQUICC 50MHZ 256PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC Ir
Datasheet
1.MPC852TVR50A.pdf
(80 pages)
Specifications of MPC852TCVR50A
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.9/3.465V
Operating Supply Voltage (min)
1.7/3.135V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
BGA
Core Size
32 Bit
Program Memory Size
8KB
Cpu Speed
50MHz
Embedded Interface Type
SPI, UART
Digital Ic Case Style
BGA
No. Of Pins
256
Supply Voltage Range
1.7V To 1.9V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC852TCVR50A
Manufacturer:
Freescale
Quantity:
486
Company:
Part Number:
MPC852TCVR50A
Manufacturer:
MOTOROLA
Quantity:
325
Company:
Part Number:
MPC852TCVR50A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Mechanical Data and Ordering Information
16.1.2
Figure 64
additional information, see the PowerQUICC™ Family Reference Manual.
68
shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For
The non-JEDEC Pinout
XTAL EXTCLK WAIT_A
VFLS_1 RSV BURST
ALE_A
PORST V
OP3
EXTAL
V
BDIP
OP0
N/C
WR
N/C
CR
V
BR
KR
2
DDL
DDL
BADDR29 BADDR28
MII_COL
GPL_A4 CS3
DSCK VFLS_0
IP_A7
IP_A0
V
OP1
CS1
CS0
AS BADDR30
TS
3
BI
DDL
DDSYN
SRESET
CE2_A GPL_A3 WE3
IP_A2
IP_A4
CS7 GPL_A2 WE2
CS2
TEA
OP2
VSSSYN1
BB
4
RSTCONF
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
VSSSYN
GPL_A5
HRESET
Figure 64. Pinout of PBGA Package—Non-JEDEC
CS5
CS6
FRZ
DP3
DP2
NOTE: This figure shows the top view of the device.
BG
TA
N/C
5
V
DP0
DDL
GPL_A0
CE_1A
IP_A3
IP_A5
DP1
D31
D30
OE
6
MII_CRS BS_A3
CLKOUT
BS_A0
IP_A1
WE1
WE0
CS4
D29
D28
D7
7
BS_A2
BS_A1
TSIZ1
IP_A6
V
D25
D24
D22
D6
DDL
8
TSIZ0
V
A28
A22
A26
A31
D26
D21
D20
D19
DDL
9
GND
D14
D15
D16
D18
A18
A30
A25
A24
A16
D5
10
D10
D11
A23
A29
A21
A20
A11
D9
D2
D3
11
IRQ1
D17
D23
D27
A19
A27
A17
A15
D1
A5
12
V
IRQ7
PD3
A14
A13
A12
A10
N/C
D12
D13
DDH
D4
13
PD13
PB31
PB30
PB28
IRQ0
TCK
PC5
PD8
PD6
N/C
A7
A9
A8
A4
D0
D8 MII_TXEN
14
PC13
PD15
PB25
TDO
PC7
PA2
PC4
PD9
PD4
PD5
N/C
TDI
A2
A6
A3
15
PC12
PD12
PD10
PB29
PA10
TMS
V
V
PC6
PD7
N/C
PA8
PA1
N/C
A1
A0
DDL
DDL
16
Freescale Semiconductor
TRST
MDIO
PC15
PA11
PB24
PB15
PD14
PD11
V
N/C
N/C
PA9
PA3
PA0
N/C
N/C
17
DDL
B
C
D
E
G
H
K
M
N
P
R
U
F
J
L
T