Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 52
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Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
40
Company:
Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
Quantity:
6 252
the programmer can double the internal clock speed from
the speed of the external clock. This feature only operates
effectively with frequencies of 10–16 MHz (20–32 MHz in-
ternal). When this bit is set to
operates in normal mode. At power-up, this feature is dis-
abled.
0
, the Z8S180/Z8L180 device
When this bit is set to
1
,
ables the low-noise option for the
This option reduces the gain in addition to reducing the out-
put drive capability to 30% of its original drive capability.
The Low Noise Crystal Option is recommended in the use
of crystals for PCMCIA applications, where the crystal may
be driven too hard by the oscillator. Setting this bit to
selected for normal operation of the
The default for this bit is
Operating restrictions for device operation are listed be-
low. If a low-noise option is required, and normal device
operation is required, use the clock multiplier feature.
0
.
Setting this bit to
and
and
ZiLOG
1
pins.
pins.
0
en-
is