Z85C3010VEG Zilog, Z85C3010VEG Datasheet - Page 62
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Z85C3010VEG
Manufacturer Part Number
Z85C3010VEG
Description
IC 10MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Specifications of Z85C3010VEG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3935
Z85C3010VEG
Z85C3010VEG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3010VEG
Manufacturer:
ZILOG
Quantity:
2 000
Table 10. Z80C30 Read/Write Timing
PS011705-0608
No
31
32
33
34
35
36
37
38
39
40
41
42
43
44
a. Units in nanoseconds (ns) unless otherwise noted.
b. Parameter does not apply to Interrupt Acknowledge transactions.
c. Parameter applies only between transactions involving the SCC.
d. Float delay is defined as the time required for a ±0.5 V change in the output with a maximum DC load and a
minimum AC load.
e. Open-drain output, measured with open-drain test load.
f. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of
TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each device
separating them in the daisy chain.
g. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
h. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing
references assume 20 V for a logic “1” and 08 V for a logic “0”.
Symbol
TdDSA(DR)
TsiEI(DSA)
ThIEI(DSA)
TdIEI(IEO)
TdAS(IEO)
TdDSA(INT)
TdDS(ASQ)
TdASQ(DS)
TwRES
TwPCI
TwPCh
TcPC
TrPC
TfPC
Figure 38
characteristics.
parameters listed in
displays Z80C30 general timing and
Parameter
DS Fall (Acknowledge) to Read Data
Valid Delay
IEI to DS Fall (Acknowledge) Setup
Time
IEI to DS Rise (Acknowledge) Hold
Time
IEI to IEO Delay
AS Rise to IEO Delay
DS Fall (Acknowledge) to INT Inactive
Delay
AS Rise to DS Fall Delay for No Reset 20
AS and DS Coincident Low for Reset
PCLK Low Width
PCLK High Width
PCLK Cycle Time
PCLK Rise Time
PCLK Fall Time
DS Rise to AS Fall Delay for No Reset 15
Figure 39
5
Table
displays the Z80C30 system timing with the associated
a
12.
(continued)
g
CMOS SCC Serial Communications Controller
Table 11
h
8 MHz
Min
80
0
150
50
50
125
lists the associated general timing
Max
140
90
200
450
1000
1000
2000
10
10
Product Specification
Electrical Characteristics
10 MHz
Min
80
0
15
15
100
40
40
100
Max
120
90
175
450
1000
1000
2000
10
10
58