Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 36

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

PS011705-0608
Read Registers
The SCC contains ten Read registers (eleven, counting the receive buffer (RR8) in each
channel). Four of these can be read to obtain status information (RR0, RR1, RR10, and
RR15). Two registers (RR12 and RR13) are read to learn the Baud Rate Generator time
constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector
modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits
(Channel A only –
Status FIFO, but is only read when WR15 D2 is set (see
Write Register 11
Write Register 9
Write Register 10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset
0
1
0
1
0
1
0
1
NRZ
FM1 (Transition = 1)
Receive Clock = RTxC Pin
Receive Clock = TRxC Pin
Receive Clock = BR Generator Output
Receive Clock = DPLL Output
NRZI
FM1 (Transition = 0)
0
1
1
0
1
1
0
0
Transmit Clock = RTxC Pin
Transmit Clock = TRxC Pin
Transmit Clock = BR Generator Output
Transmit Clock = DPLL Output
0
0
1
1
Figure 18. Write Register Bit Functions
0
1
0
1
TRxC Out = Xtal Output
TRxC Out = Transmit Clock
TRxC Out = BR Generator Output
TRxC Out = DPLL Output
Figure
VIS
NV
MIE
Status High/Status Low
DLC
Software INTACK Enable
TRxC O/I
6-Bit/8-Bit Sync
Loop Mode
Abort/Flag on Underrun
Mark/Flag Idle
Go Active on Poll
CRC Preset I/O
RTxC Xtal/No Xtal
19). RR6 and RR7 contain the information in the SDLC Frame
CMOS SCC Serial Communications Controller
Write Register 13
Write Register 14
Write Register 12
Write Register 15
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reset Missing Clock
Set Source = BR Generator
Set FM Mode
Null Command
Enter Search Mode
Disable DPLL
Set Source = RTxC
Set NRZI Mode
Figure 19
TC7
TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
TC0
TC1
TC2
TC3
TC4
TC5
TC6
BR Generator Enable
BR Generator Source
DTR/Request Function
Auto Echo
Local Loopback
Sync/Hunt IE
CTS IE
0
Zero Count IE
SDLC FIFO Enable
DCD IE
Tx Underrun/EOM IE
Break/Abort IE
Product Specification
Time Constant
Lower Byte of
Upper Byte of
Time Constant
and
Functional Description
Figure
20).
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