Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 30
![IC 8MHZ Z8500 CMOS SCC 44-PLCC](/photos/6/57/65795/269-44-plcc_sml.jpg)
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3008VSG
Manufacturer:
Zilog
Quantity:
800
Company:
Part Number:
Z85C3008VSG
Manufacturer:
MAX
Quantity:
74
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2.3.2 Z85X30 Write Cycle Timing
The write cycle timing for the Z85X30 is shown in Figure 2-
6. The address on A//B and D//C, as well as the data on
D7-D0, is latched by the coincidence of /WR and /CE ac-
tive. /CE must remain Low and /INTACK must remain High
throughout the cycle. A write cycle with D//C High does not
disturb the state of the pointers and a write cycle with D//C
Low resets the pointers to zero after the internal operation
is complete.
2.3.3 Z85X30 Interrupt Acknowledge Cycle Timing
The interrupt acknowledge cycle timing for the Z85X30 is
shown in Figure 2-7. The state of /INTACK is latched by
A//B, D//C
/INTACK
/INTACK
D7-D0
D7-D0
/CE
/WR
/RD
Note: Dotted line is ESCC only.
Figure 2-7. Z85X30 Interrupt Acknowledge Cycle Timing
Figure 2-6. Z85X30 Write Cycle Timing
See Note
Historically, the NMOS/CMOS version latched the data
bus on the falling edge of /WR. However, many CPUs do
not guarantee that the data bus is valid at the time when
the /WR pin goes low, so the data bus timing was modified
to allow a maximum delay from the falling edge of /WR to
the latching of the data bus. On the Z85230, the AC Timing
parameter #29 TsDW(WR), Write Data to /WR falling min-
imum, has been changed to: /WR falling to Write Data Val-
id maximum. Refer to the AC Timing Characteristic section
of the Z85230 Product Specification for more information
regarding this change.
the rising edge of PCLK (AC Spec #10). While /INTACK is
Low, the state of A//B, /CE, D//C, and /WR are ignored.
Address Valid
Data Valid
Vector
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2-11
2
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