CY8CTMG200-24LQXIT Cypress Semiconductor Corp, CY8CTMG200-24LQXIT Datasheet - Page 240

• Manufacturer Part Number: CY8CTMG200-24LQXIT
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-24LQXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-UQFN Exposed Pad, 24-HUQFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I2C_SCR
21.3.52 I2C_SCR
This register is used by the slave to control the flow of data bytes and to keep track of the bus state during a transfer.
Bits in this register are held in reset until one of the enable bits in I2C_CFG is set. In the table above, note that the reserved
bit is a grayed table cell and not described in the bit description section below. Reserved bits must always be written with a
value of ‘0’. For additional information, refer to the
Bit
7
5
4
3
2
1
0
240
Individual Register Names and Addresses:
I2C_SCR : 0,D7h
Access : POR
Bit Name
0,D7h
Bus Error
Stop Status
ACK
Address
Transmit
LRB
Byte Complete
Name
I
2
Bus Error
C Status and Control Register
RC : 0
7
6
Description
0
1
0
1
Acknowledge Out. Bit is automatically cleared by hardware upon a Byte Complete event.
0
1
0
1
Bit is set by firmware to define the direction of the byte transfer. Any Start detect or a write to the Start
or Restart generate bits when operating in master mode also clears the bit.
0
1
Last Received Bit. The value of the 9
the receiver. Any Start detect or a write to the Start or Restart generate bits when operating in master
mode also clears the bit.
0
1
Transmit/Receive Mode:
0
Transmit Mode:
1
Receive Mode:
1
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Status bit. It must be cleared by firmware by writing a ‘0’ to the bit position. It is never
cleared by the hardware.
A misplaced Start or Stop condition was detected.
Status bit. It must be cleared by firmware with a write of ‘0’ to the bit position. It is never
cleared by the hardware.
A Stop condition was detected.
NACK the last received byte.
ACK the last received byte
Status bit. It must be cleared by firmware with a write of ‘0’ to the bit position.
The received byte is a slave address.
Receive mode.
Transmit mode.
Last transmitted byte was ACK’ed by the receiver.
Last transmitted byte was NACK’ed by the receiver.
No completed transmit/receive since last cleared by firmware. Any Start detect or a write to
the Start or Restart generate bits when operating in master mode also clears the bit.
Eight bits of data have been transmitted and an ACK or NACK has been received.
Eight bits of data have been received.
Stop Status
RC : 0
5
Register Definitions on page 122
0,D7h
RW : 0
ACK
4
th
bit in a Transmit sequence, which is the acknowledge bit from
Address
RC : 0
3
in the I2C Slave chapter .
Transmit
RW : 0
2
RC : 0
LRB
1
Byte Complete
RC : 0
0
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