CY7C53120E2-10AXIT Cypress Semiconductor Corp, CY7C53120E2-10AXIT Datasheet - Page 7
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CY7C53120E2-10AXIT
Manufacturer Part Number
CY7C53120E2-10AXIT
Description
IC PROCESSOR NEURON 44LQFP
Manufacturer
Cypress Semiconductor Corp
Series
Neuron®r
Datasheet
1.CY7C53150-20AXI.pdf
(16 pages)
Specifications of CY7C53120E2-10AXIT
Applications
Network Processor
Core Processor
Pipelined
Program Memory Type
FLASH (2 kB), ROM (10 kB)
Controller Series
CY7C531xx
Ram Size
2K x 8
Interface
Serial
Number Of I /o
11
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C53120E2-10AXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Programmable Hysteresis Values
(Expressed as differential peak-to-peak voltages in terms of V
Programmable Glitch Filter Values
(Receiver (end-to-end) filter values expressed as transient pulse
suppression times)
Notes
Document #: 38-10001 Rev. *G
6. Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value.
7. Must be disabled if data rate is 1.25 Mbps or greater.
8. Receiver input, V
9. CPO and CP1 inputs each 0.60 Vp – p, 1.25 MHz sine wave 180° out of phase with each other as shown in
10. t
Hysteresis
Filter (F)
PLH
0
1
2
3
: Time from input switching states from low to high to output switching states. t
0
1
2
3
4
5
6
7
[6]
D
= V
Min
120
240
480
0.019 V
0.040 V
0.061 V
0.081 V
0.101 V
0.121 V
0.142 V
0.162 V
10
V
CP0
hys
– V
Min
CP1
DD
DD
DD
DD
DD
DD
DD
DD
, at least 200 mV greater than hysteresis levels. See
1500
Typ
410
800
75
0.027 V
0.054 V
0.081 V
0.108 V
0.135 V
0.162 V
0.189 V
0.216 V
V
hys
Typ
[7]
DD
DD
DD
DD
DD
DD
DD
DD
1350
2600
Max
140
700
0.035 V
0.068 V
0.101 V
0.135 V
0.169 V
0.203 V
0.236 V
0.270 V
V
hys
Max
Unit
ns
ns
ns
ns
DD
DD
DD
DD
DD
DD
DD
DD
DD
)
PHL
Receiver
(Worst case across hysteresis)
Differential Receiver (End-to-End) Absolute
Symmetry
: Time from input switching states from high to low to output switching states.
Filter (F)
Figure
Filter (F)
0
0
1
2
3
3.
V
Figure 3. Receiver Input Waveform
[8]
DD
CP0
CP1
⎮
[9, 10]
V
(End-to-End) Absolute Asymmetry
/2
CP0 – CP1
hys
Hysteresis (H)
+ 200 mV
Figure
0
CY7C53150, CY7C53120
⎮
10. V
≥
Max (t
DD
= 5.00 V ± 5%.
≤ 3 ns
PLH
150
250
400
35
Max (t
– t
PHL
PLH
24
)
– t
PHL
Page 7 of 16
)
Unit
Unit
ns
ns
ns
ns
ns
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