CY7C68013-100AXC Cypress Semiconductor Corp, CY7C68013-100AXC Datasheet - Page 16

• Manufacturer Part Number: CY7C68013-100AXC
• Description: IC MCU USB PERIPH HI SPD 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013-100AXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.12.6
Table 3-6. Default High-Speed Alternate Settings
Note:
3.13
3.13.1
The FX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic.
The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally
controlled transfers.
3.13.2
The FX2 endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instan-
taneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Since they are physically the same
memory, no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available
to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dual-port in the 8051-I/O
domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can
be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96
Megabytes/s (48 MHz).
In Slave (S) mode, the FX2 accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. Each endpoint can individually be selected for byte
or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected
width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface
can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in
synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.
3.13.3
An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively,
an externally supplied clock of 5 MHz – 48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured
to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or
externally sourced.
3.14
The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013
to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and
Utopia.
Document #: 38-08012 Rev. *C
3.
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Alternate Setting
Default High-Speed Alternate Settings
External FIFO interface
Architecture
Master/Slave Control Signals
GPIF and FIFO Clock Rates
GPIF
64
0
0
0
0
0
0
0
64
512 bulk
512 bulk
512 bulk out (2×)
512 bulk out (2×)
512 bulk in (2×)
512 bulk in (2×)
[3]
[3]
[1, 2]
1
64
64 int
64 int
512 int out (2×)
512 bulk out (2×)
512 int in (2×)
512 bulk in (2×)
2
64
64 int
64 int
512 iso out (2×)
512 bulk out (2×)
512 iso in (2×)
512 bulk in (2×)
CY7C68013
3
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