AN2136SC Cypress Semiconductor Corp, AN2136SC Datasheet - Page 332

• Manufacturer Part Number: AN2136SC
• Description: IC MCU 8051 8K RAM 24MHZ 44QFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2136SC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1309

latched and must remain active until serviced.
C.4.4 Interrupt Latency
Interrupt response time depends on the current state of the 8051. The fastest response time is 5
instruction cycles: 1 to detect the interrupt, and 4 to perform the LCALL to the ISR.
The maximum latency (13 instruction cycles) occurs when the 8051 is currently executing a
RETI instruction followed by a MUL or DIV instruction. The 13 instruction cycles in this case
are: 1 to detect the interrupt, 3 to complete the RETI, 5 to execute the DIV or MUL, and 4 to
execute the LCALL to the ISR. For the maximum latency case, the response time is 13 x 4 =
52 CLK24 cycles.
C.4.5 Single-Step Operation
The 8051 interrupt structure provides a way to perform single-step program execution. When
exiting an ISR with an RETI instruction, the 8051 will always execute at least one instruction
of the task program. Therefore, once an ISR is entered, it cannot be re-entered until at least
one program instruction is executed.
To perform single-step execution, program one of the external interrupts (for example,INT0)
to be level-sensitive and write an ISR for that interrupt the terminates as follows:
The CPU enters the ISR when the INT0# pin goes low, then waits for a pulse on INT0#. Each
time INT0# is pulsed, the CPU exits the ISR, executes one program instruction, then re-enters
the ISR.
C.5
The 8051 RESET pin is internally connected to an EZ-USB register bit that is controllable
through the USB host. See Chapter 10, "EZ-USB Resets" for details.
C.6
C.6.1 Idle Mode
An instruction that sets the IDLE bit (PCON.0) causes the 8051 to enter idle mode when that
instruction completes. In idle mode, CPU processing is suspended, and internal registers
maintain their current data. When the 8051 core is in idle, the EZ-USB core enters suspend
C - 36
JNB
JB
RETI
Reset
Power Saving Modes
TCON.1,$
TCON.1,$
; wait for high on INT0# pin
; wait for low on INT0# pin
; return for ISR
Appendix C: 8051 Hardware Description
EZ-USB TRM v1.9