AN2131SC Cypress Semiconductor Corp, AN2131SC Datasheet
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The EZ-USB The EZ-USB The EZ-USB The EZ-USB The EZ-USB Integrated Circuit Integrated Circuit Integrated Circuit Integrated Circuit Integrated Circuit Technical Reference ...
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... Cypress Semiconductor Corporation product could create a situation where personal injury or death may occur. Should Buyer purchase or use Cypress Semiconductor Corporation products for any such unintended or unauthorized application, Buyer shall indemnify and hold Cypress Semiconductor Corporation and its officers, ...
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Development Kit — Getting Started Documentation for the EZ-USB™ Xcelerator™ Development it. Includes an overview of the kit, descriptions of kit components with installation instruc- tions, and details about the development board. Technical Reference Documentation of the EZ-USB controller. Includes ...
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Technical Reference Manual Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Reset and Power Management .............................................................. 1-15 1.17 EZ-USB Product Family ....................................................................... 1-16 1.18 Summary of AN2122, AN2126 Features ............................................. 1-16 1.19 Revision ID ........................................................................................... 1-17 1.20 Pin Descriptions .................................................................................... 1-18 2 EZ-USB CPU .................................................................................. 2-1 2.1 Introduction ............................................................................................. 2-1 ...
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ID1, ID0 ................................................................................. 4-10 4.8 Sending I2C Data .................................................................................. 4-10 4.9 Receiving I2C Data ............................................................................... 4-11 4.10 I2C Boot Loader ................................................................................... 4-12 5 EZ-USB Enumeration and ReNumeration ..................................5-1 5.1 Introduction ............................................................................................. 5-1 5.2 The Default USB Device ........................................................................ 5-2 ...
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Get Status ................................................................................. 7-7 7.3.2 Set Feature ............................................................................. 7-10 7.3.3 Clear Feature ......................................................................... 7-12 7.3.4 Get Descriptor ....................................................................... 7-12 7.3.4.1 7.3.4.2 7.3.4.3 7.3.5 Set Descriptor ........................................................................ 7-16 7.3.6 Set Configuration ................................................................... 7-19 7.3.7 Get Configuration .................................................................. 7-19 7.3.8 Set ...
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USB Core Interrupts ............................................................................... 9-1 9.3 Wakeup Interrupt .................................................................................... 9-2 9.4 USB Signaling Interrupts ........................................................................ 9-4 9.5 SUTOK, SUDAV Interrupts ................................................................... 9-8 9.6 SOF Interrupt .......................................................................................... 9-9 9.7 Suspend Interrupt .................................................................................... 9-9 9.8 USB RESET Interrupt ............................................................................ 9-9 9.9 ...
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UART Operation - AN2122, AN2126 ............................. 12-14 12.9 Isochronous Control/Status Registers ................................................. 12-14 2 12. Registers ....................................................................................... 12-16 12.11 Interrupts ............................................................................................. 12-19 12.12 Endpoint 0 Control and Status Registers ............................................ 12-29 12.13 Endpoint 1-7 Control and ...
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Figure 1-1. AN2131S (44 pin) Simplified Block Diagram .................................................. 1-2 Figure 1-2. AN2131Q (80 pin) Simplified Block Diagram .................................................. 1-3 Figure 1-3. USB Packets ...................................................................................................... 1-4 Figure 1-4. Two Bulk Transfers, IN and OUT ..................................................................... 1-7 Figure 1-5. An Interrupt ...
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Figure 6-9. Interrupt Service Routine (ISR) for Endpoint 6-OUT ..................................... 6-19 Figure 6-10. Background Program Transfers Endpoint 6-OUT Data to Endpoint 6-IN ...... 6-20 Figure 6-11. Initialization Routine ........................................................................................ 6-21 Figure 6-12. Autopointer Registers ...................................................................................... 6-23 Figure 6-13. Use of ...
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Figure 12-1. Register Description Format ............................................................................ 12-2 Figure 12-2. Bulk Data Buffers ............................................................................................ 12-3 Figure 12-3. Isochronous Data FIFOs .................................................................................. 12-4 Figure 12-4. Isochronous Byte Counts ................................................................................. 12-6 Figure 12-5. CPU Control and Status Register ..................................................................... 12-8 Figure 12-6. IO ...
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Figure 13-5. Fast Transfer Mode Block Diagram ................................................................. 13-6 Figure 13-6. Fast Transfer Read Timing [Mode 00] ............................................................ 13-7 Figure 13-7. Fast Transfer Write Timing [Mode 00] ............................................................ 13-7 Figure 13-8. Fast Transfer Read Timing [Mode 01] ............................................................ 13-8 Figure ...
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Table 1-1. USB PIDs............................................................................................................ 1-4 Table 1-2. EZ-USB Series 2100 Family ............................................................................ 1-16 Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function ................................................. 1-23 Table 2-1. EZ-USB Interrupts .............................................................................................. 2-4 Table 2-2. Added Registers and Bits.................................................................................... 2-6 Table 4-1. IO ...
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Table 7-1. The Eight Bytes in a USB SETUP Packet .......................................................... 7-5 Table 7-2. How the 8051 Handles USB Device Requests (ReNum=1) ............................... 7-6 Table 7-3. Get Status-Device (Remote Wakeup and Self-Powered Bits) ............................ 7-8 Table 7-4. Get Status-Endpoint (Stall ...
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Table 13-3. Program Memory Read..................................................................................... 13-2 Table 13-4. Data Memory Read........................................................................................... 13-2 Table 13-5. Data Memory Write .......................................................................................... 13-3 Table 13-6. Fast Data Write ................................................................................................. 13-3 Table 13-7. Fast Data Read .................................................................................................. 13-3 EZ-USB TRM v1.9 List of Tables xiii ...
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List of Tables EZ-USB TRM v1.9 ...
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Introducing EZ-USB 1.1 Introduction Like a well designed automobile or appliance, a USB peripheral’s outward simplicity hides internal complexity. There’s a lot going on “under the hood” USB device, which gives the user a new level of ...
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This chapter introduces some key USB concepts and terminology that should make read- ing the rest of this Technical Reference Manual easier. 1.2 EZ-USB Block Diagrams + GND USB USB Connector Transceiver Figure 1-1. AN2131S (44 pin) Simplified ...
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D+ D- GND USB USB Connector Transceiver Figure 1-2. AN2131Q (80 pin) Simplified Block Diagram Figure 1-2 illustrates the An2131Q, an 80-pin version of the EZ-USB family. In addition to the 24 IO pins, it contains a 16-bit address ...
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Tokens and PIDs In this manual, you will read statements like, “When the host sends an IN token...” or “The device responds with an ACK.” What do these terms mean? A USB transaction consists of data packets identified by ...
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PID that arrives with the data, either DATA0 or DATA1. When sending data, the host or device sends alternating DATA0-DATA1 PIDs. By comparing the Data PID with the state of the internal toggle bit, the host or device can detect ...
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PC. If USB had been defined as peer-to-peer, every USB device would have required more intelligence, raising cost. Here are two important consequences of the “host is master” concept: 1.5.1 Receiving Data from the Host ...
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EZ-USB Transfer Types USB defines four transfer types. These match the requirements of different data types delivered over the bus. (Section 1.13, "EZ-USB Endpoints" explains how the EZ-USB family supports the four transfer types.) 1.8.1 Bulk Transfers D A ...
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Isochronous Transfers Token Packet Isochronous data is time-critical and used for streaming data like audio and video. Time of delivery is the most important requirement for isochronous data. In every USB frame, a ...
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Control transfers consist of two or three stages. The SETUP stage contains eight bytes of USB CONTROL data. An optional DATA stage contains more data, if required. The STATUS (or handshake) stage allows the device to indicate successful completion of ...
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The USB Core Payload Data Token Packet Data Packet D+ D- Every USB device has a Serial Interface Engine ...
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One of the most important features of the EZ-USB family is that it is soft. Instead of requiring ROM or other fixed memory, it contains internal program/data RAM that is downloaded over the USB itself to give the device its ...
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The 8051 communicates with the SIE using a set of registers, which occupy the top of the on-chip RAM address space. These registers are grouped and described by function in individual chapters of this reference manual, and summarized in register ...
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EZ-USB Bulk Endpoints Bulk endpoints are unidirectional—one endpoint address per direction. Therefore end- point 2-IN is addressed differently than endpoint 2-OUT. Bulk endpoints use maximum packet sizes (and therefore buffer sizes 16, 32 bytes. EZ-USB ...
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EZ-USB Interrupt Endpoints Interrupt endpoints are almost identical to bulk endpoints. Fourteen EZ-USB endpoints (EP1-EP7, IN, and OUT) may be used as interrupt endpoints. Interrupt endpoints have maximum packet sizes up to 64, and contain a “polling interval” byte ...
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Interrupts The EZ-USB enhanced 8051 adds seven interrupt sources to the standard 8051 interrupt system. Three of the added interrupts are used internally, and the others are available on device pins. INT2 is used for all USB interrupts. INT3 ...
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EZ-USB Product Family The EZ-USB family is available in various pinouts to serve different system requirements and costs. Table 1-2 shows the feature set for each member of the EZ-USB Series 2100 Family. Table 1-2. EZ-USB Series 2100 Family ...
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Variants There are two 48-pin devices: AN2122T AN2126T The four extra pins are used as follows: • PA7, PA6, and PA0 are GPIO pins. This makes five of the eight PORTA pins available (all except PA1-PA3). • CPU12MHZ - ...
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Pin Descriptions Figures 1-9 through 1-13 are pin descriptions by package type. Table 1-3 describes the pins by pin function ...
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GND 1 CLK24 2 3 GND GND 4 GND 5 GND 6 AGND 7 XIN 8 9 XOUT 10 AVCC 11 VCC Figure 1-10. 44-pin PQFP Package with Port B (AN2121S, AN2122S, and AN2131S) ...
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GND 1 2 CLK24 3 GND 4 GND 5 GND GND 6 AGND 7 XIN 8 9 XOUT AVCC 10 11 VCC Figure 1-11. 44-pin Package with Data Bus (AN2125S, AN2126S, AN2135S, and AN2136) ...
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GND 1 CLK24 2 GND 3 GND 4 GND 5 GND 6 AGND 7 8 PA7/RxD1OUT XIN 9 XOUT 10 AVCC 11 VCC Analog VCC and GND Extra pins in 48-pin package Digital GND Digital ...
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GND 1 CLK24 2 GND 3 GND 4 5 GND GND 6 AGND 7 PA7/RxD1OUT 8 XIN 9 XOUT 10 AVCC 11 12 VCC 13 14 Analog VCC and GND Extra pins in 48-pin package Digital GND Digital ...
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S ...
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S 24 N/A N/A N/A N N/A N ...
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S 71 N/A N/A N/A N N/A N N/A N/A 75 N/A N ...
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S 44 24 N N N N/A 29 N/A 52 ...
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S 55 31 N ...
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S ...
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Introduction The EZ-USB built-in microprocessor, an enhanced 8051 core, is fully described in Appen- dices A-C. This chapter introduces the processor, its interface to the EZ-USB core, and describes architectural differences from a standard 8051. 2.2 8051 Enhancements The ...
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EZ-USB Enhancements The EZ-USB chip provides additional enhancements outside the 8051. These include: • Fast external transfers (Autopointer, Fast Transfer Mode) • Vectored USB interrupts (Autovector) • Separate buffers for SETUP and DATA portions of a CONTROL transfer. • ...
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EZ-USB Internal RAM Like the standard 8051, the EZ-USB 8051 core contains 128 bytes of register RAM at 00- 7F, and a partially populated SFR register space at 80-FF. An additional 128 indirectly addressed registers (sometimes called “IDATA”) are ...
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An output enable bit that causes the IO pin to be driven from the output latch. • An alternate function bit that determines whether the pin is general special 8051 or EZ-USB function. The SFRs associated ...
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Power Control The EZ-USB core implements a power-down mode that allows used in USB bus powered devices that must draw no more than 500 A when suspended. Power control is accomplished using a combination of 8051 ...
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SFRs The EZ-USB family was designed to keep 8051 coding as standard as possible, to allow easy integration of existing 8051 software development tools. The added 8051 SFR regis- ters and bits are summarized in Table 2-2. 8051 Enhancements ...
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Internal Bus Members of the EZ-USB family that provide pins to expand 8051 memory provide sepa- rate non-multiplexed 16-bit address and 8-bit data busses. This differs from the standard 8051, which multiplexes eight device pins between three sources: IO ...
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Page 2-8 Chapter 2. EZ-USB CPU EZ-USB TRM v1.9 ...
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Introduction EZ-USB devices divide RAM into two regions, one for code and data, and the other for USB buffers and control registers. 7FFF Registers/Bulk Buffers 7B40 27FF Data (RD/WR) RAM If ISODISAB=1 2000 1FFF Registers/Bulk Buffers 1B40 1B3F Data ...
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Memory Figure 3-1 illustrates the two internal EZ-USB RAM regions. 6,976 bytes of general-pur- pose RAM occupy addresses 0x0000-0x1B3F. This RAM is loadable by the EZ-USB 2 core bus EEPROM, and contains 8051 code and ...
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Figure 3-3. Unused Bulk Endpoint Buffers (Shaded) Used as Data Memory In the example shown in Figure 3-3, only endpoints 0-IN through 3-IN are used for the USB function, so the data RAM (shaded) can be extended to 0x1D7F. If ...
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Expanding EZ-USB Memory The 80-pin EZ-USB package provides a 16-bit address bus, an 8-bit bus, and memory control signals PSEN#, RD#, and WR#. These signals are used to expand EZ-USB memory. Inside EZ-USB FFFF 8000 Registers(RD,WR) 7B40 2000 1FFF ...
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The internal block at 0x7B40-0x7FFF (labeled “Registers”) contains the bulk buffer mem- ory and EZ-USB control registers. As previously mentioned, they are aliased at 0x1B40- 0x1FFF to allow adding unused bulk buffer RAM to general-purpose memory. 8051 code should access ...
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Inside EZ-USB FFFF 8000 Registers(RD,WR) 7B40 2000 1FFF 1F3F Unused Bulk Buffers (RD,WR) 1B40 Data (RD,WR) 0000 Note populate data memory here--RD#, WR#, CS# and OE# are inactive. Figure 3-5. EZ-USB Memory Map with EA=1 When EA=1 ...
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EZ-USB ROM Versions The EZ-USB 8-KB Masked ROM and 32-KB Masked ROM memory maps are shown in Figures 3-6 and 3-7. Inside EZ-USB FFFF 8000 Registers(RD,WR) 7B40 2000 0800 07FF Data (RD,WR) 0000 Note populate data ...
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Inside EZ-USB FFFF 8000 7FFF Registers(RD,WR) 7B40 1000 0FFF Data (RD,WR) 0000 Note populate data memory here, but no RD# or WR# strobes are generated. Note populate code memory here, but no PSEN# strobe ...
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EZ-USB Input/Output 4.1 Introduction The EZ-USB chip provides two input-output systems: • A set of programmable IO pins 2 • A programmable I C Controller This chapter begins with a description of the programmable IO pins, and shows how ...
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IO Ports OE OUT PINS Figure 4-1. EZ-USB Input/Output Pin The EZ-USB family implements its IO ports using memory-mapped registers. This is in contrast to a standard, which uses SFR bits for input/output. Figure 4-1 shows the basic structure ...
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Table 4-1. IO Pin Functions for PORTxCFG=0 and PORTxCFG=1 PORTxCFG bit = 0 Signal Signal PA0 T0OUT PA1 T1OUT PA2 OE# PA3 CS# PA4 FWR# PA5 FRD# PA6 RxD0OUT PA7 RxD1OUT PB0 PB1 T2EX PB2 RxD1 PB3 TxD1 PB4 INT4 ...
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Alternate Function Output OE OUT reg PINS PORTCFG=0 (port) Figure 4-2. Alternate Function is an OUTPUT Referring to Figure 4-2, when PORTCFG=0, the IO port is selected. In this case the alter- nate function (shaded) is disconnected and the pin ...
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IO Port Registers PORTACFG RxD1out RxD0out OUTA D7 D6 PINSA D7 D6 OEA D7 D6 PORTBCFG T2OUT INT6 OUTB D7 D6 PINSB D7 D6 OEB D7 D6 PORTCCFG RD WR OUTC D7 D6 PINSC D7 D6 OEC D7 D6 ...
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I C Controller 2 The USB core contains controller for boot loading and general-purpose I interface. This controller uses the SCL (Serial Clock) and SDA (Serial Data) pins. I2C Controller describes how the boot load ...
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Multiple I C Bus Masters never a slave. However, the 8051 can detect a second master by checking for BERR=1 (Section 4.7, "Status Bits"). start SDA SA3 SA2 SCL 1 2 Figure 4-6. Addressing The first ...
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I2CS START STOP LASTRD I2DAT The 8051 uses the two registers shown in Figure 4-7 to conduct I transfers data to and from the I 2 12CS register controls I C ...
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I2DAT until the STOP bit returns low. In the 2122/2126 only, an interrupt request is available to signal that STOP bit transmission is complete. 4.6.3 LASTRD 2 To read data over the I C bus the SCL ...
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ACK bit at the same time it sets DONE=1. The ACK bit should be ignored for read trans- fers on the bus. 4.7.3 BERR 2 This bit indicates bus error. BERR=1 indicates that there was bus contention, ...
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Receiving I C Data To read a multiple-byte data record, follow these steps: 1. Set the START bit. 2. Write the peripheral address and direction=1 (for read) to I2DAT. 3. Wait for DONE=1*. If BERR=1 or ACK=0, terminate ...
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I C Boot Loader When the EZ-USB chip comes out of reset, the EZ-USB boot loader checks for the pres- 2 ence of an EEPROM on its I C bus EEPROM is detected, the loader reads ...
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Table 4-2. Strap Boot EEPROM Address Lines to These Values Bytes 16 128 256 This EEPROM does not have address pins 2 The I C controller performs a three-step test at power-on to determine whether a one-byte- ...
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The results of this power-on test are reported in the ID1 and ID0 bits, as shown in Table 4-3. Table 4-3. Results of Power-On I ID1 Other EEPROM devices (with device address of 1010) can be ...
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EZ-USB Enumeration and ReNumeration 5.1 Introduction The EZ-USB chip is soft. 8051 code and data is stored in internal RAM, which is loaded from the host using the USB interface. Peripheral devices that use the EZ-USB chip can operate ...
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Another Use for the Default USB Device The Default USB Device is established at power-on to set up a USB device capable of downloading firmware into EZ-USB RAM. Another useful feature of the EZ-USB default device is that 8051 code ...
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For purposes of downloading 8051 code, the Default USB Device requires only CON- TROL endpoint zero. Nevertheless, the USB default machine is enhanced to support other endpoints as shown in Figure 5-1 (note the alternate settings 1 and 2). This ...
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EZ-USB Core Response to EP0 Device Requests Table 5-2 shows how the EZ-USB core responds to endpoint zero requests when ReNum=0. Table 5-2. How the EZ-USB Core Handles EP0 Requests When ReNum=0 bRequest 0x00 Get Status/Device 0x00 Get Status/Endpoint ...
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As shown in Table 5-2, after enumeration, the EZ-USB core responds to the following host requests. • Set or clear an endpoint stall (Set/Clear Feature-Endpoint). • Read the stall status for an endpoint (Get_Status_Endpoint). • Set/Read an 8-bit configuration number ...
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Byte Field 0 bmRequest 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH These requests are always handled by the EZ-USB core (ReNum=0 or 1). This means that 0xA0 is reserved by the EZ-USB chip, ...
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Enumeration Modes When the EZ-USB chip comes out of reset, the EZ-USB core makes a decision about how to enumerate based on the contents of an external EEPROM on its I shows the choices. In Table 5-5, PID means ...
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The Other Half of the I C Story 2 The EZ-USB I C controller serves two purposes. First, as described in this chapter, it manages the serial EEPROM interface that operates automatically at power-on to deter- mine the enumeration ...
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Reminder The EZ-USB core uses the Table 5-6 data for enumeration only if the ReNum bit is zero. If ReNum=1, enumeration data is supplied by 8051 code. 5.7 Serial EEPROM Present, First Byte is 0xB0 Table 5-7. EEPROM Data Format ...
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Serial EEPROM Present, First Byte is 0xB2 If, at power-on, the EZ-USB core detects an EEPROM connected to its I value 0xB2 at address 0; the EZ-USB core loads the EEPROM data into EZ-USB RAM. It also sets the ...
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One or more data records follow, starting at EEPROM address 7. The maximum value of Length H is 0x03, allowing a maximum of 1,023 bytes per record. Each data record con- sists of a length, a starting address, and a ...
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DISCON DISCOE The logic for the DISCON and DISCOE bits is shown in Figure 5-2. To simulate a USB disconnect, the 8051 writes the value 00001010 to USBCS. This floats the DISCON# pin, and provides an internal DISCON signal to ...
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Multiple ReNumerations The 8051 can ReNumerate an isochronous endpoint’s bandwidth requests by trying various descriptor values and ReNumerating. 5.11 Default Descriptor Tables 5-9 through 5-19 show the descriptor data built into the EZ-USB core. The tables are presented in ...
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Table 5-10. USB Default Configuration Descriptor Offset Field 0 bLength 1 bDescriptorType 2 wTotalLength (L) 3 wTotalLength (H) 4 bNumInterfaces 5 bConfigurationValue 6 iConfiguration 7 bmAttributes 8 MaxPower The configuration descriptor includes a total length field (offset 2-3) that encompasses ...
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Table 5-12. USB Default Interface 0, Alternate Setting 1 Descriptor Offset Field 0 bLength 1 bDescriptorType 2 bInterfaceNumber 3 bAlternateSetting 4 bNumEndpoints 5 bInterfaceClass 6 bInterfaceSubClass 7 bInterfaceProtocol 8 iInterface Interface 0, alternate setting 1 has thirteen endpoints, whose individual ...
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Table 5-14. USB Default Interface 0, Alternate Setting 1, Bulk Endpoint Descriptors Offset Field 0 bLength 1 bDescriptorType 2 bEndpointAddress 3 bmAttributes 4 wMaxPacketSize (L) 5 wMaxPacketSize (H) Maximum Packet Size - High 6 bInterval 0 bLength 1 bDescriptorType 2 ...
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Table 5-14. USB Default Interface 0, Alternate Setting 1, Bulk Endpoint Descriptors Offset Field 0 bLength 1 bDescriptorType 2 bEndpointAddress 3 bmAttributes 4 wMaxPacketSize (L) 5 wMaxPacketSize (H) Maximum Packet Size - High 6 bInterval Interface 0, alternate setting 1 ...
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Table 5-15. USB Default Interface 0, Alternate Setting 1, Isochronous Endpoint Descriptors Offset Field 0 bLength 1 bDescriptorType 2 bEndpointAddress 3 bmAttributes 4 wMaxPacketSize (L) 5 wMaxPacketSize (H) Maximum Packet Size - High 6 bInterval 0 bLength 1 bDescriptorType 2 ...
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Interface 0, alternate setting 1 has six isochronous endpoints with maximum packet sizes of 16 bytes. This is a low bandwidth setting. Table 5-16. USB Default Interface 0, Alternate Setting 2 Descriptor Offset Field 0 bLength 1 bDescriptor Type 2 ...
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Table 5-18. USB Default Interface 0, Alternate Setting 2, Bulk Endpoint Descriptors Offset Field 0 bLength 1 bDescriptor Type 2 bEndpointAddress 3 bmAttributes 4 wMaxPacketSize (L) 5 wMaxPacketSize (H) Maximum Packet Size - High 6 bInterval 0 bLength 1 bDescriptorType ...
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Table 5-19. USB Default Interface 0, Alternate Setting 2, Isochronous Endpoint Descriptors Offset Field 0 bLength 1 bDescriptorType 2 bEndpointAddress 3 bmAttributes 4 wMaxPacketSize (L) 5 wMaxPacketSize (H) Maximum Packet Size - High 6 bInterval 0 bLength 1 bDescriptorType 2 ...
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Page 5-22 Chapter 5. EZ-USB CPU EZ-USB TRM v1.9 ...
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EZ-USB Bulk Transfers 6.1 Introduction Payload Data Token Packet Data Packet Figure 6-1. Two BULK Transfers, IN and OUT EZ-USB ...
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The USB specification allows maximum packet sizes of 8, 16, 32 bytes for bulk data, and bytes for interrupt data. EZ-USB provides the maximum 64 bytes of buffer space for each of its sixteen endpoints ...
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Registers Associated with a Bulk IN endpoint Initialization IN07VAL Endpoint Valid (1=valid) USBPAIR o67 o45 Endpoint Pairing (1=paired) IN07IEN Interrupt Enable (1=enabled) Busy and Stall IN2CS Control & Status Registers Associated with ...
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Bulk IN Transfers ... Token Packet (INnBC loaded ... ...
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IN tokens (4) and (7) until the data is ready. Eventually, the 8051 fills the endpoint buffer with data, and then loads the endpoint’s byte count register (INnBC) with the number of bytes in the packet (6). Loading the byte ...
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The 8051 now loads the next 64 bytes into IN2BUF and then loads the EPINBC register with 64 for the next two transfers. For the last portion of the transfer, the 8051 loads the final 28 bytes into IN2BUF, and ...
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Payload ... Data Token Packet Data Packet (OUTnBC loaded, OUTnBSY= ...
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NAK, indicating busy (6). The data at (5) is shaded to indicate that the USB core discards it, and does not over-write the data in the endpoint’s OUT buffer. The host continues to send OUT tokens (4, ...
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This pairs the IN2BUF and IN3BUF buffers, although the 8051 accesses the IN2BUF buffer only. The 8051 sets PR2IN=1 (in the USBPAIR register) to enable pairing, sets IN2VAL=1 (in the IN07VAL register) to ...
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Paired OUT Endpoint Status OUTnBSY=1 indicates that both endpoint buffers are empty, and no data is available to the 8051. When OUTnBSY=0, either one or both of the buffers holds USB OUT data. The 8051 can keep an internal ...
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Chapter 3 gives full details of the EZ-USB memory map. Note AN2122 endpoint memory starts at 0x1C00 and AN2126 endpoint memory starts at address 0x7C00. Note Uploads or Downloads ...
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The IO bit selects the endpoint direction (1=IN, 0=OUT), and the EP2-EP1-EP0 bits select the endpoint number. The Q bit, which is read-only, indicates the state of the data toggle for the selected endpoint. Writing R=1 sets the data toggle ...
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Polled Bulk Transfer Example The following code illustrates the EZ-USB registers used for a simple bulk transfer. In this example, 8051 register R1 keeps track of the number of endpoint 2-IN transfers and register R2 keeps track of the ...
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The code at lines 2-7 fills the endpoint 2-IN buffer with 64 bytes of a decrementing count. Two 8-bit counts are initialized to zero at lines 9 and 10. An endpoint 2-IN transfer is armed at lines 11-13, which load ...
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Bulk Endpoint Interrupts All USB interrupts activate the 8051 INT 2 interrupt. If enabled, INT2 interrupts cause the 8051 to push the current program counter onto the stack, and then execute a jump to loca- tion 0x43, where the ...
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The vector values are four bytes apart. This allows the programmer to build a jump table to each of the interrupt service routines. Note that the jump table must begin on a page (256 byte) boundary because the first vector ...
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Set up the jump table. USB_Jump_Table: This table contains all of the USB interrupts, even though only the jumps for endpoint 2 are used for the example convenient to include this table in any USB application that ...
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Write the INT2 interrupt vector. ; ----------------- ; Interrupt Vectors ; ----------------- org 43h ljmp USB_Jump_Table 3. Write the interrupt service routine. Put it anywhere in memory and the jump table in step 1 will automatically jump to it. ...
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Write the endpoint 2 transfer program. 1 loop: jnb got_EP2_data,loop 2 clr got_EP2_data The user sent bytes to OUT2 endpoint using the USB Control Panel Find out how many bytes were sent. 6 ...
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OUT2BC is used as a loop counter transfer the exact number of bytes that were received over endpoint 2-OUT. When the transfer is complete, the program loads the endpoint 2-IN byte count register IN2BC with the number ...
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Enumeration Note The code in this example is complete, and runs on the EZ-USB chip. You may be wonder- ing about the missing step, which reports the endpoint characteristics to the host during the enumeration process. The reason this ...
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The Autopointer Bulk endpoint data is available in 64-byte buffers in EZ-USB RAM. In some cases it is preferable to access bulk data as a FIFO register rather than as a RAM. The EZ-USB core provides a special data ...
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The 8051 code example in Figure 6-13 uses the Autopointer to transfer a block of eight data bytes from the endpoint 4 OUT buffer to internal 8051 memory. Init: mov dptr,#AUTOPTRH mov a,#HIGH(OUT4BUF) movx @dptr,a mov dptr,#AUTOPTRL mov a,#LOW(OUT4BUF) movx ...
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Note The Autopointer works only with internal program/data RAM. It does not work with memory outside the chip, or with internal RAM that is made available when ISO- DISAB=1. See Section 8.9.1, "Disable ISO" for a description of the ISODISAB ...
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EZ-USB Endpoint Zero 7.1 Introduction Endpoint Zero has special significance in a USB system CONTROL endpoint, and is required by every USB device. Only CONTROL endpoints accept special SETUP tokens that the host uses to signal ...
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Control Endpoint EP0 SETUP Stage bytes Setup Data Token Packet Data Packet SUTOK Interrupt Core sets ...
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The STATUS stage consists of an empty data packet with the opposite direction of the data stage there was no data stage. This empty data packet gives the device a chance to ACK or NAK the ...
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USB registers starting at SETUPDAT. The EZ-USB core takes care of any re-tries if it finds any errors in the SETUP data. These two interrupt request bits are set by the EZ- USB core, and must be cleared by firmware. ...
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Two bits in the USBIEN (USB Interrupt Enable) register enable the SETUP Token (SUTOKIE) and SETUP Data interrupts. The actual interrupt request bits are in the USBIRQ (USB Interrupt Requests) register. They are called STOKIR (SETUP Token Interrupt Request) and ...
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Table 7-2. How the 8051 Handles USB Device Requests (ReNum=1) bRequest Name 0x00 Get Status 0x01 Clear Feature 0x02 (reserved) 0x03 Set Feature 0x04 (reserved) 0x05 Set Address 0x06 Get Descriptor 0x07 Set Descriptor 0x08 Get Configuration SUDAV Interrupt 0x09 ...
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Get Status The USB Specification version 1.0 defines three USB status requests. A fourth request interface, is indicated in the spec as “reserved.” The four status requests are: • Remote Wakeup (Device request) • Self-Powered (Device request) ...
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As Figure 7-4 illustrates, the 8051 responds to the SUDAV interrupt by decoding the eight bytes the EZ-USB core has copied into RAM at SETUPDAT. The 8051 answers a Get_Status request (bRequest=0) by loading two bytes into the IN0BUF buffer ...
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Each bulk endpoint (IN or OUT) has a STALL bit in its Control and Status register (bit 0). If the CPU sets this bit, any requests to the endpoint return a STALL handshake rather than ACK or NAK. The Get ...
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Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH Get_Status/Interface is easy: the 8051 returns two zero bytes through IN0BUF and clears the HSNAK bit. The requested bytes are shown as ...
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Table 7-7. Set Feature-Endpoint (Stall) Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH The only Set_Feature/Endpoint request presently defined in the USB Specification is to stall an endpoint. The 8051 ...
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Clear Feature Clear Feature is used to disable remote wakeup or to clear a stalled endpoint. Table 7-8. Clear Feature-Device (Clear Remote Wakeup Bit) Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 ...
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EP0-IN) such information as what device driver to load, how many endpoints it has, its different configurations, alternate settings it may use, and informative text strings about the device. The EZ-USB core provides a special Setup Data Pointer to ...
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The CONTROL transaction starts in the usual way, with the EZ-USB core transferring the eight bytes in the SETUP packet into RAM at SETUPDAT and activating the SUDAV interrupt request. The 8051 decodes the Get_Descriptor request, and responds by clearing ...
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This constitutes the second phase of the three-phase CONTROL transfer. The core Packetizes the data into multiple data transfers as necessary. 4. Automatically checks for errors and re-transmits data packets if necessary. 5. Responds to the third (handshake) phase ...
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Get Descriptor-String Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH Configuration and string descriptors are handled similarly to device descriptors. The 8051 firmware reads byte 2 of the SETUP ...
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Table 7-14. Set Descriptor-Configuration Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH ...
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Configurations, Interfaces, and Alternate Settings Configurations, Interfaces, and Alternate Settings A USB device has one or more configu- ration. Only one configuration is active at any time. A configuration has one or more inter- face, all of which are concurrently ...
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Set Configuration Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH When the host issues the Set_Configuration request, the 8051 saves the configuration number (byte 2 in Table Table 7-16), ...
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Set Interface This confusingly named USB command actually sets and reads back alternate settings for a specified interface. USB devices can have multiple concurrent interfaces. For example a device may have an audio system that supports different sample rates, ...
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Get Interface Table 7-19. Get Interface (Actually, Get Alternate Setting AS for interface IF) Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH The 8051 simply returns the alternate setting ...
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Sync Frame Byte Field 0 bmRequestType 1 bRequest 2 wValueL 3 wValueH 4 wIndexL 5 wIndexH 6 wLengthL 7 wLengthH The Sync_Frame request is used to establish a marker in time so the host and USB device can synchronize ...
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Firmware Load The USB endpoint zero protocol provides a mechanism for mixing vendor-specific requests with the previously described standard device requests. Bits 6:5 of the bmRe- quest field are set to 00 for a standard device request, and to ...
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Page 7-24 Chapter 7. EZ-USB CPU EZ-USB TRM v1.9 ...
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EZ-USB Isochronous Transfers 8.1 Introduction Isochronous endpoints typically handle time-critical, streamed data that is delivered or consumed in byte-sequential order. Examples might be audio data sent to a DAC over USB, or teleconferencing video data sent from a camera ...
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Isochronous IN Transfers IN transfers travel from device to host. Figure 8-2 shows the EZ-USB registers and bits associated with isochronous IN transfers. Registers Associated with an ISO IN endpoint Initialization INISOVAL Endpoint Valid ...
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The EZ-USB core uses the ISOSEND0 bit to determine what to do if: • The 8051 does not load any bytes to an INnDATA register during the previous frame, and • token for that endpoint arrives from the ...
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Registers Associated with an ISO OUT endpoint Initialization OUTISOVAL Endpoint Valid (1=valid) OUT15ADDR FIFO Start Address (see text) USBIEN SOFIE (1=enabled) Figure 8-3. Isochronous OUT Registers 8.3.1 ...
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To respond to the SOF interrupt, the 8051 clears the USB interrupt (8051 INT2), and clears the SOFIR bit by writing one to it. Then, the 8051 reads data from the appropriate OUTnDATA FIFO register(s). The 8051 can check an ...
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Table 8-1. Isochronous Endpoint FIFO Starting Address Registers Register Function OUT8ADDR Endpoint 8 OUT Start Address OUT9ADDR Endpoint 9 OUT Start Address OUT10ADDR Endpoint 10 OUT Start Address OUT11ADDR Endpoint 11 OUT Start Address OUT12ADDR Endpoint 12 OUT Start Address ...
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EP8INSZ equ 256 0100 EP8OUTSZ equ 256 0010 EP9INSZ equ 16 0010 EP9OUTSZ equ 16 0010 EP10INSZ equ 16 0010 EP10OUTSZ equ 16 0000 EP11INSZ equ 0 0000 EP11OUTSZ equ 0 0000 EP12INSZ equ 0 0000 EP12OUTSZ equ 0 ...
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Isochronous Transfer Speed The amount of data USB can transfer during a 1-ms frame is slightly more than 1,000 bytes per frame (1,500 bytes theoretical, without accounting for USB overhead and bus utilization). A device’s actual isochronous transfer bandwidth ...
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Fast Transfers EZ-USB has a special fast transfer mode for applications that use external FIFOs con- nected to the EZ-USB data bus. These applications typically require very high transfer speeds in and out of EZ-USB endpoint buffers. DPTR The ...
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Fast Bulk Transfers The EZ-USB core provides a special auto-incrementing data pointer that makes the fast transfer mechanism available for bulk transfers. The 8051 loads a 16-bit RAM address into the AUTOPTRH/L registers, and then accesses RAM data as a ...
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Fast Reads DPTR Figure 8-9. Fast Transfer, Outside Memory to EZ-USB Fast reads are illustrated in Figure 8-9. When the fast mode is enabled, the DPTR points to an isochronous OUT FIFO register, and the 8051 executes the “movx ...
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RMOD1-RMOD0 for read strobes and WMOD1-WMOD0 for write strobes, as shown in Figure 8-11 (write) and Figure 8-12 (read). Note When using the fast transfer feature, be sure to enable the FRD# and FWR# strobe sig- nals in the PORTACFG ...
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The timing choices for fast write pulses (FWR#) are shown in Figure 8-11. The 8051 can extend the output data and widths of these pulses by setting cycle stretch values greater than zero in the 8051 Clock Control Register CKCON ...
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FRD# strobes[00] and [01], along with the OSC24 clock signal are typically used to con- nect to an external synchronous FIFO. The on-clock-wide read strobe ensures that the FIFO address advances only once per clock. The second strobe [01] is ...
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The 1,024 byte transfer would take 403 s, less than half of the 1-ms USB frame time. If still faster time is required, the routine can be modified to put more of the MOVX ...
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ISOCTL register bits shown as MBZ (must be zero) must be written with zeros. The PPSTAT bit toggles every SOF, and may be written with any value (no effect). Therefore, to disable the isochronous endpoints, the 8051 should write the ...
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ISO IN Response with No Data The ISOSEND0 bit (bit 7 in the USBPAIR register) is used when the EZ-USB chip receives an isochronous IN token while the IN FIFO is empty. If ISOSEND0=0 (the default value) the EZ-USB ...
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Page 8-18 Chapter 8. EZ-USB CPU EZ-USB TRM v1.9 ...
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Introduction The EZ-USB enhanced 8051 responds to the interrupts shown in Table 9-1. Interrupt sources that are not present in the standard 8051 are shown as checked in the “New” col- umn. The three interrupts used by the EZ-USB ...
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USB Signaling - These include 16 bulk endpoint interrupts, three interrupts not specific to a particular endpoint (SOF), Suspend, USB Reset), and two interrupts for CONTROL transfers (SUTOK, SUDAV). These interrupts share the USB interrupt (INT2). The AN2122/26 versions have ...
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EICON.5 ; enable Resume interrupt The 8051 reads the RESUME interrupt request bit in EICON.4, and clears the interrupt request by writing a zero to EICON.4. Resume_isr: clr EICON.4 reti EZ-USB TRM v1.9 ; clear the 8051 W/U ; ...
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USB Signaling Interrupts Figure 9-2 shows the 21 USB requests that share the 8051 USB (INT2) interrupt. The bot- tom IRQ, EP7-OUT, is expanded in the diagram to show the logic associated with each USB interrupt request. Vector 05, ...
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Referring to the logic inside the dotted lines, each USB interrupt source has an interrupt request latch. The EZ-USB core sets an IRQ bit, and the 8051 clears an IRQ bit by writing a “1” to it. The output of ...
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Figure 9-3 illustrates a typical USB ISR for endpoint 2-IN. USB_ISR: push dps push dpl push dph push dpl1 push dph1 push acc ; mov a,EXIF clr acc.4 mov EXIF,a ; mov dptr,#IN07IRQ mov a,#00000100b movx @dptr (perform ...
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IN07IRQ Endpoints 0-7 IN Interrupt Requests IN7IR IN6IR IN5IR OUT07IRQ Endpoints 0-7 OUT Interrupt Requests OUT7IR OUT6IR OUT5IR USBIRQ IN07IEN Endpoints 0-7 IN Interrupt Enables ...
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The USBIEN and USBIRQ registers control the first five interrupts shown in Figure 9-2. The IN07IEN and OUT07 registers control the remaining 16 USB interrupts, which corre- spond to the 16 bulk endpoints IN0-IN7 and OUT0-OUT7. The 21 USB interrupts ...
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SOF Interrupt Figure 9-6. A Start Of Frame (SOF) Packet USB Start of Frame interrupt requests occur every millisecond. When the EZ-USB core receives an SOF packet, it copies the eleven-bit frame number (FRNO in Figure 9-6) into the ...
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The EZ-USB core sets an endpoint’s interrupt request bit when the endpoint’s busy bit (in the endpoint CS register) goes low, indicating that the endpoint buffer is available to the 8051. For example, when endpoint 4-OUT receives a data packet, ...
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Table 9-3. A Typical USB Jump Table 9.11 Autovector Coding A detailed example of a program that uses Autovectoring is presented in Section 6.14, "Interrupt Bulk Transfer Example." The coding steps are summarized here. To employ EZ-USB Autovectoring: 1. Insert ...
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Code the jump table with jump instructions to each individual USB interrupt ser- vice routine. This table has two important requirements, arising from the format of the AVEC byte (zero-based, with 2 LSBs set to 0): • It must ...
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I C Interrupt EZ-USB 8051 DONE I2DAT register Interrupt Request I2CS START STOP I2DAT D7 D6 Figure 9-8. I Chapter 4, "EZ-USB Input/Output" describes the 8051 interface to the EZ-USB ...
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In some situations, the host may send IN tokens before the 8051 has loaded and armed an IN endpoint. To alert the 8051 that an IN endpoint is being pinged, the AN2122/26 add a set of interrupts, one per IN ...
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I C STOP Complete Interrupt - (AN2122/AN2126 only) I2CMODE The I C interrupt includes one additional interrupt source in the AN2122/AN2126, a 1-0 transition of ...
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The two registers that the 8051 uses to control I 2 USB family interrupt request occurs on INT3 whenever the DONE bit (I2CS.0) makes a 0-to-1 transition. This interrupt signals the 8051 that the I for another ...
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Introduction The EZ-USB chip has three resets: • A Power-On Reset (POR), which turns on the EZ-USB chip in a known state. • An 8051 reset, controlled by the EZ-USB core. • A USB bus reset, sent by the ...
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Vcc through capacitor and to GND through a 10-K resistor (Figure 10-1). The oscillator and PLL are unaffected by the state of the RESET pin. The CLK24 signal is active while RESET = HI. When ...
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From Table 10-1, at power-on: • Endpoint data buffers and byte counts are un-initialized (1,2). • The 8051 is held in reset, and the CLK24 pin is enabled (3). • All port pins are configured as input ports (4-6). • ...
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RAM Download Once enumerated, the host can download code into the EZ-USB RAM using the “Firm- ware Load” vendor request (Chapter 7, "EZ-USB Endpoint Zero"). The last packet loaded writes 0 to the CPUCS register, which clears the 8051 ...
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Reset,” and should not be confused with the POR described in Section 10.2, "EZ-USB Power-On Reset (POR)." This discussion applies only to the condition where the EZ-USB chip is powered, and the ...
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Table 10-2. EZ-USB States After a USB Bus Reset Item 1 Endpt Data 2 Byte Counts 3 CPUCS 4 PORT Configs 5 PORT Registers 6 PORT OEs 7 Interrupt Enables 8 Interrupt Reqs 9 Bulk IN C/S 10 Bulk OUT ...
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Note from item 12 that the ReNum bit is unchanged after a USB bus reset. Therefore device has ReNumerated and loaded a new personality, it retains the new personality through a USB bus reset. 10.6 EZ-USB Disconnect Table ...
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The function address is reset to zero (13). • The configuration is reset to zero (19). • Alternate settings are reset to zero (20). 10.7 Reset Summary Table 10-4. Effects of Various EZ-USB Resets (“U” Means “Unaffected”) Resource 8051 ...
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EZ-USB Power Management 11.1 Introduction The USB host can suspend a device to put it into a power-down mode. When the USB signals a SUSPEND operation, the EZ-USB chip goes through a sequence of steps to allow the 8051 ...
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Suspend No USB activity for 3 msec. Figure 11-2. EZ-USB Suspend Sequence A USB device recognizes SUSPEND bus idle (“J”) state. The EZ-USB core alerts the 8051 by asserting the USB (INT2) interrupt and ...
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The 8051 code responds to the SUSPEND interrupt by taking the following steps: 1. Performs any necessary housekeeping such as shutting off external power-con- suming devices. 2. Sets bit 0 of the PCON SFR (Special Function Register). This has two ...
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The EZ-USB oscillator re-starts when: • USB bus activity resumes (shown as “USB Resume” in Figure 11-3), or • External logic asserts the EZ-USB WAKEUP# pin low. After an oscillator stabilization time, the EZ-USB core asserts the 8051 Resume interrupt ...
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Note If your design does not use remote wakeup, tie the WAKEUP# pin high. Holding the WAKEUP# pin low inhibits the EZ-USB chip from suspending. When a USB device is suspended, the hub driver is tri-stated, and the bus pullup ...
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Page 11-6 Chapter 11. EZ-USB Power Management EZ-USB TRM v1.9 ...
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Introduction This section describes the EZ-USB registers in the order they appear in the EZ-USB mem- ory map. The registers are named according to the following conventions. Most registers deal with endpoints. The general register format is DDDnFFF, where: ...
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Other Conventions USB Indicates a global (not endpoint-specific) USB function. ADDR Is an address. VAL Means “valid.” FRAME Is a frame count. PTR Is an address pointer. Register Name bitname bitname bitname R, W access R, W ...
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Bulk Data Buffers INnBUF,OUTnBUF Endpoint 0-7 IN/OUT Data Buffers R/W R/W R See Table 12-1 for individual endpoint buffer addresses. Table 12-1. Bulk Endpoint Buffer Memory Addresses Address 1F00-1F3F ...
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Isochronous Data FIFOs OUTnDATA EP8OUT-EP15OUT FIFO Registers INnDATA EP8IN-EP15IN FIFO Registers See Table 12-2 ...
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Sixteen addressable data registers hold data from the eight isochronous IN endpoints and the eight isochronous OUT endpoints. Reading a Data Register reads a Receive FIFO byte (USB OUT data); writing a Data Register loads a Transmit FIFO byte (USB ...
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Isochronous Byte Counts OUTnBCH INnBCL BC7 BC6 BC5 See Table 12-3 for individual endpoint buffer addresses. Figure ...
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The EZ-USB core uses the byte count registers to report isochronous data payload sizes for OUT data transferred from the host to the USB core. Ten bits of byte count data allow payload sizes up to 1,023 bytes. A byte ...