AT43USB326-AC Atmel, AT43USB326-AC Datasheet - Page 7

• Manufacturer Part Number: AT43USB326-AC
• Description: IC USB KEYBOARD CTRLR HUB 48LQFP
• Manufacturer: Atmel
• Series: AVR®r

Specifications of AT43USB326-AC

• Applications: Keyboard Controller
• Core Processor: AVR
• Program Memory Type: Mask ROM (16 kB)
• Controller Series: AT43USB
• Ram Size: 512 x 8
• Interface: USB
• Number Of I /o: 32
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The General-
purpose
Register File
3313D–USB–04/06
instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is
a downloadable SRAM or a mask programmed ROM.
With the relative jump and call instructions, the whole 24K address space is directly accessed.
Most AVR instructions have a single 16-bit word format. Every program memory address con-
tains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on
the stack. The stack is effectively allocated in the general data SRAM, and consequently, the
stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the Stack Pointer (SP) in the reset routine (before subroutines or
interrupts are executed). The 10-bit SP is read/write accessible in the I/O space.
The 1-Kbyte data SRAM can be easily accessed through the five different addressing modes
supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps. A flexi-
ble interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt
vector table at the beginning of the program memory. The interrupts have priority in accor-
dance with their interrupt vector position. The lower the interrupt vector address, the higher the
priority.
Table 1. AVR CPU General-purpose Working Register
All register operating instructions in the instruction set have direct and single cycle access to
all registers. The only exception is the five constant arithmetic and logic instructions SBCI,
SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load
Register
R0
R1
R2
..
R13
R14
R15
R16
R17
..
R26
R27
R28
R29
R30
R31
Address
$00
$01
$02
$0D
$0E
$0F
$10
$11
$1A
$1B
$1C
$1D
$1E
$1F
Comment
X-register low byte
X-register high byte
Y-register low byte
Y-register high byte
Z-register low byte
Z-register high byte
AT43USB326
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