CY8C20236A-24LKXI Cypress Semiconductor Corp, CY8C20236A-24LKXI Datasheet - Page 28
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CY8C20236A-24LKXI
Manufacturer Part Number
CY8C20236A-24LKXI
Description
MCU 8K FLASH 1K SRAM 16UQFN
Manufacturer
Cypress Semiconductor Corp
Series
CapSense® Controllersr
Datasheet
1.CY8C20536A-24PVXI.pdf
(38 pages)
Specifications of CY8C20236A-24LKXI
Program Memory Type
FLASH (8 kB)
Package / Case
16-UQFN, 16-µQFN
Applications
Capacitive Sensing
Core Processor
M8C
Controller Series
CY8C20xx6A
Ram Size
1K x 8
Interface
I²C, SPI
Number Of I /o
13
Voltage - Supply
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8C20x36A
Core
M8C
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
10
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3280-20X66
Minimum Operating Temperature
- 40 C
Program Memory Size
8 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C20236A-24LKXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY8C20236A-24LKXIT
Manufacturer:
CPRESS13
Quantity:
4 988
Part Number:
CY8C20236A-24LKXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
AC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 32. AC Programming Specifications
Document Number: 001-54459 Rev. **
T
T
T
T
F
T
T
T
T
T
T
Symbol
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
ERASEB
WRITE
DSCLK
DSCLK3
DSCLK2
XRST3
SCLK (P1[1])
SDATA (P1[0])
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK 3.6 < Vdd
Data Out Delay from Falling Edge of SCLK 3.0 ≤ Vdd ≤ 3.6
Data Out Delay from Falling Edge of SCLK 1.71 ≤ Vdd ≤ 3.0
External Reset Pulse Width after Power Up Required to enter programming mode
T
RSCLK
Description
T
SSCLK
T
FSCLK
Figure 13. AC Waveform
T
HSCLK
when coming out of sleep
Conditions
CY8C20X36A/46A/66A/96A
T
Min
263
DSCLK
40
40
1
1
0
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
Max
130
20
20
18
25
60
85
–
–
8
–
Page 28 of 38
Units
MHz
ms
ms
ns
ns
ns
ns
ns
ns
ns
μs
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