ADE7566ASTZF16 Analog Devices Inc, ADE7566ASTZF16 Datasheet - Page 72
![IC ENERGY METER 1PHASE 64-LQFP](/photos/6/60/66065/505-64-lqfp_sml.jpg)
ADE7566ASTZF16
Manufacturer Part Number
ADE7566ASTZF16
Description
IC ENERGY METER 1PHASE 64-LQFP
Manufacturer
Analog Devices Inc
Specifications of ADE7566ASTZF16
Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (16 kB)
Controller Series
ADE75xx
Ram Size
512 x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Ic Function
Single Phase Energy Measurement IC
Supply Voltage Range
3.13V To 3.46V, 2.4V To 3.7V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. V
current delivered to the load, respectively. Therefore, the apparent
power (AP) = V
phase angle between the current and the voltage.
Equation 31 gives an expression of the instantaneous power
signal in an ac system with a phase shift.
Figure 76 illustrates the signal processing for the calculation of
the apparent power in the ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569.
The apparent power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and setting the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channel waveform
sampling modes, the waveform data is available at sample rates
of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
v t
t i
p
p
( )
( )
( )
(
t
t
)
=
=
=
=
V
v
2
2
(
rms
t
V
I
)
rms
rms
I
rms
×
rms
t i
× I
sin(
sin( )
(
cos(
)
rms
rms
ω
ω
. This equation is independent of the
and I
t
θ
t
)
+
−
θ
V
)
rms
rms
are the effective voltage and
I
V
I
rms
rms
rms
cos(
CURRENT RMS SIGNAL – i(t)
VOLTAGE RMS SIGNAL – v(t)
0x1CF68C
0x1CF68C
2
ω
0x00
0x00
t
+
θ
)
Figure 76. Apparent Power Signal Processing
(28)
(29)
(30)
(31)
Rev. B | Page 72 of 152
VARMSCFCON
The gain of the apparent energy can be adjusted by using the
multiplier and by writing a twos complement, 12-bit word to the
VAGAIN register (VAGAIN[11:0], Address 0x1F). Equation 32
shows how the gain adjustment is related to the contents of the
VAGAIN register.
For example, when 0x7FF is written to the VAGAIN register, the
power output is scaled up by 50% (0x7FF = 2047d, 2047/2
Similarly, 0x800 = −2047d (signed twos complement) and power
output is scaled by −50%. Each LSB represents 0.0244% of the
power output. The apparent power is calculated with the current
and voltage rms values obtained in the rms blocks of the
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register to
calibrate and eliminate the dc component in the rms value (see the
Current Channel RMS Calculation and the Voltage Channel
RMS Calculation section). The voltage and current channels
rms values are then multiplied together in the apparent power
signal processing. Because no additional offsets are created in
the multiplication of the rms values, there is no specific offset
compensation in the apparent power signal processing. The
offset compensation of the apparent power measurement is
done by calibrating each individual rms measurement.
Output VAGAIN =
VAGAIN
⎛
⎜
⎝
Apparent
DIGITAL-TO-FREQUENCY
0x1A36E2
CONVERTER
APPARENT POWER
SIGNAL (P)
Power
TO
×
⎧ +
⎨
⎩
1
VAGAIN
2
12
⎫
⎬
⎭
⎞
⎟
⎠
12
= 0.5).
(32)