CY8C20546A-24PVXI Cypress Semiconductor Corp, CY8C20546A-24PVXI Datasheet - Page 29
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CY8C20546A-24PVXI
Manufacturer Part Number
CY8C20546A-24PVXI
Description
IC MCU 16K FLASH 2K SRAM 48SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CapSense® Controllersr
Datasheet
1.CY8C20536A-24PVXI.pdf
(38 pages)
Specifications of CY8C20546A-24PVXI
Program Memory Type
FLASH (16 kB)
Package / Case
48-SSOP
Applications
Capacitive Sensing
Core Processor
M8C
Controller Series
CY8C20xx6A
Ram Size
2K x 8
Interface
I²C, SPI
Number Of I /o
36
Voltage - Supply
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8C20x46A
Core
M8C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
31
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3280-20X66
Minimum Operating Temperature
- 40 C
Program Memory Size
16 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8C20546A-24PVXI
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CY8C20546A-24PVXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 33. AC Characteristics of the I2C SDA and SCL Pins
Document Number: 001-54459 Rev. **
F
T
T
T
T
T
T
T
T
T
Note
11. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement t
SCLI2C
HDSTAI2C
LOWI2C
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
SPI2C
Symbol
SDA
SCL
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line t
SCL Clock Frequency
Hold Time (repeated) START Condition. After this period, the first clock pulse is
generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
S
T
rmax
HDSTAI2C
T
LOWI2C
+ t
SU;DAT
T
Figure 14. Definition for Timing for Fast/Standard Mode on the I
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
HDDATI2C
T
T
HIGHI2C
SUDATI2C
Description
T
SUSTAI2C
Sr
T
HDSTAI2C
SU;DAT
CY8C20X36A/46A/66A/96A
≥ 250 ns must then be met. This automatically be the
T
SUSTOI2C
T
SPI2C
Min
250
4.0
4.7
4.0
4.7
4.0
4.7
0
0
–
Standard
2
C Bus
Mode
Max
100
P
–
–
–
–
–
–
–
–
–
T
BUFI2C
100
Fast Mode
Min
0.6
1.3
0.6
0.6
0.6
1.3
0
0
0
[11]
S
Page 29 of 38
Max
400
50
–
–
–
–
–
–
–
–
Units
kHz
μs
μs
μs
μs
μs
μs
μs
ns
ns
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