CY7C68013A-100AXI Cypress Semiconductor Corp, CY7C68013A-100AXI Datasheet - Page 59

• Manufacturer Part Number: CY7C68013A-100AXI
• Description: IC MCU USB PERIPH HI SPD 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-100AXI

• Program Memory Type: ROMless
• Package / Case: 100-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Package: 100TQFP
• Device Core: 8051
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2263; CY7C68013A-100AXI

Package Diagrams
13. PCB Layout Recommendations
Follow these recommendations to ensure reliable high perfor-
mance operation:
■
■
■
■
■
Document #: 38-08032 Rev. *M
Note
24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High
Four layer impedance controlled boards are required to
maintain signal quality.
Specify impedance targets (ask your board vendor what they
can achieve).
To control impedance, maintain trace widths and trace spacing.
Minimize stubs to minimize reflected signals.
Connections between the USB connector shell and signal
ground must be near the USB connector.
Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
PIN A1 CORNER
A
C
G
B
D
E
F
H
[24]
-C-
1
Figure 40. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901)
SEATING PLANE
2
SIDE VIEW
(continued)
3
5.00±0.10
TOP VIEW
4
5
6
6
8
■
■
■
■
■
Bypass and flyback caps on VBus, near connector, are recom-
mended.
DPLUS and DMINUS trace lengths should be kept to within 2
mm of each other in length, with preferred length of 20 to
30 mm.
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to split under these traces.
Do not place vias on the DPLUS or DMINUS trace routing.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
PACKAGE WEIGHT: 0.02 grams
REFERENCE JEDEC: MO-195C
-B-
0.10(4X)
-A-
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
BOTTOM VIEW
8
7
Ø0.05 M C
Ø0.30±0.05(56X)
Ø0.15 M C A B
6
5.00±0.10
5
0.50
3.50
4
001-03901-*B
3
2
1
A1 CORNER
A
C
G
B
D
E
F
H
Page 59 of 62
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