CY7C68013A-56PVXI Cypress Semiconductor Corp, CY7C68013A-56PVXI Datasheet - Page 23
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CY7C68013A-56PVXI
Manufacturer Part Number
CY7C68013A-56PVXI
Description
IC MCU USB PERIPH HI SPD 56-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56PVXI
Program Memory Type
ROMless
Package / Case
56-SSOP
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C/USART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3684
Minimum Operating Temperature
- 40 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1944-5
CY7C68013A-56PVXI
CY7C68013A-56PVXI
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Manufacturer
Quantity
Price
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Table 3-1. FX2LP Pin Descriptions (continued)
Document #: 38-08032 Rev. *T
TQFP
Port A
128
34
99
35
12
82
83
84
11
1
TQFP
100
100
28
77
10
67
68
69
11
–
SSOP
56
49
12
40
41
42
11
–
–
5
QFN
56
42
54
33
34
35
–
–
5
4
VFBGA
8B
1C
2C
2B
8G
6G
56
8F
–
BKPT
RESET#
EA
XTALIN
XTALOUT
CLKOUT on
CY7C68013A
and
CY7C68014A
------------------
PE1 on
CY7C68015A
and
CY7C68016A
PA0 or
INT0#
PA1 or
INT1#
PA2 or
SLOE or
Name
-----------
Output
Output
Type
Input
Input
Input
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
Default
12 MHz
----------
(PA0)
(PA1)
(PA2)
N/A
N/A
N/A
N/A
L
I
I
I
I
Breakpoint. This pin goes active (HIGH) when the 8051
address bus matches the BPADDRH/L registers and
breakpoints are enabled in the BREAKPT register
(BPEN = 1). If the BPPULSE bit in the BREAKPT
register is HIGH, this signal pulses HIGH for eight
12-/24-/48 MHz clocks. If the BPPULSE bit is LOW, the
signal remains HIGH until the 8051 clears the BREAK
bit (by writing 1 to it) in the BREAKPT register.
Active LOW Reset. Resets the entire chip. See section
2.9 ”Reset and Wakeup” on page 7 for more details.
External Access. This pin determines where the 8051
fetches code between addresses 0x0000 and 0x3FFF.
If EA = 0 the 8051 fetches this code from its internal
RAM. IF EA = 1 the 8051 fetches this code from external
memory.
Crystal Input. Connect this signal to a 24 MHz
parallel-resonant, fundamental mode crystal and load
capacitor to GND.
It is also correct to drive XTALIN with an external
24-MHz square wave derived from another clock
source. When driving from an external source, the
driving signal should be a 3.3V square wave.
Crystal Output. Connect this signal to a 24 MHz
parallel-resonant, fundamental mode crystal and load
capacitor to GND.
If an external clock is used to drive XTALIN, leave this
pin open.
CLKOUT: 12-, 24- or 48 MHz clock, phase locked to the
24 MHz input clock. The 8051 defaults to 12 MHz
operation. The 8051 may three-state this output by
setting CPUCS.1 = 1.
------------------------------------------------------------------------
PE1 is a bidirectional I/O port pin.
Multiplexed pin whose function is selected by
PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input
signal, which is either edge triggered (IT0 = 1) or level
triggered (IT0 = 0).
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input
signal, which is either edge triggered (IT1 = 1) or level
triggered (IT1 = 0).
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with program-
mable polarity (FIFOPINPOLAR.4) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Description
Page 23 of 67
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