CY7C68013A-56BAXC Cypress Semiconductor Corp, CY7C68013A-56BAXC Datasheet - Page 27
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CY7C68013A-56BAXC
Manufacturer Part Number
CY7C68013A-56BAXC
Description
IC MCU USB PERIPH HI SPD 56VFBGA
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56BAXC
Program Memory Type
ROMless
Package / Case
56-VFBGA
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3684
Minimum Operating Temperature
0 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Package
56FBGA
Device Core
8051
Family Name
FX2LP
Maximum Speed
48 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2264
CY7C68013A-56BAXC
Q2748398
CY7C68013A-56BAXC
Q2748398
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68013A-56BAXC
Manufacturer:
ON
Quantity:
2 900
Company:
Part Number:
CY7C68013A-56BAXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C68013A-56BAXC
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
CY7C68013A-56BAXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Table 3-1. FX2LP Pin Descriptions (continued)
Document #: 38-08032 Rev. *T
TQFP
128
112
113
114
115
69
4
5
6
7
8
9
TQFP
100
90
91
92
93
54
3
4
5
6
7
8
SSOP
56
36
–
–
–
–
8
9
–
–
–
–
QFN
56
29
–
–
–
–
1
2
–
–
–
–
VFBGA
1A
1B
7H
56
–
–
–
–
–
–
–
–
PE4 or
RXD1OUT
PE5 or
INT6
PE6 or
T2EX
PE7 or
GPIFADR8
RDY0 or
SLRD
RDY1 or
SLWR
RDY2
RDY3
RDY4
RDY5
CTL0 or
FLAGA
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input
Input
Input
Input
Input
Input
O/Z
Default
(PE4)
(PE5)
(PE6)
(PE7)
N/A
N/A
N/A
N/A
N/A
N/A
H
I
I
I
I
Multiplexed pin whose function is selected by the
PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1.
When RXD1OUT is selected and UART1 is in Mode 0,
this pin provides the output data for UART1 only when
it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
Multiplexed pin whose function is selected by the
PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The
INT6 pin is edge-sensitive, active HIGH.
Multiplexed pin whose function is selected by the
PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2.
T2EX reloads timer 2 on its falling edge. T2EX is active
only if the EXEN2 bit is set in T2CON.
Multiplexed pin whose function is selected by the
PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable
polarity (FIFOPINPOLAR.3) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable
polarity (FIFOPINPOLAR.2) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
RDY2 is a GPIF input signal.
RDY3 is a GPIF input signal.
RDY4 is a GPIF input signal.
RDY5 is a GPIF input signal.
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status
flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
CY7C68013A, CY7C68014A
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Description
Page 27 of 67
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