CY7C64713-128AXC Cypress Semiconductor Corp, CY7C64713-128AXC Datasheet - Page 41

• Manufacturer Part Number: CY7C64713-128AXC
• Description: IC MCU USB EZ FX1 16KB 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-128AXC

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1678; CY7C64713-128AXC

The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK.
Table 23. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
There is no specific timing requirement that needs to be met for
asserting the PKTEND pin concerning asserting SLWR.
PKTEND is asserted with the last data value clocked into the
FIFOs or thereafter. The only consideration is that the set up time
t
Although there are no specific timing requirements for asserting
PKTEND in relation to SLWR, there exists a specific case
condition that needs attention. When using the PKTEND to
commit a one byte or word packet, an additional timing
requirement must be met when the FIFO is configured to operate
in auto mode and it is necessary to send two packets back to
back:
■
■
Document #: 38-08039 Rev. *F
t
t
t
t
SPE
IFCLK
SPE
PEH
XFLG
A full packet (defined as the number of bytes in the FIFO
meeting the level set in the AUTOINLEN register) committed
automatically followed by
A short one byte or word packet committed manually using the
PKTEND pin.
PKTEND
FIFOADR
IFCLK
SLWR
DATA
and the hold time t
Parameter
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
PEH
Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram
for PKTEND must be met.
t
SFA
t
IFCLK
>= t
t
SFD
SWR
X-4
t
FDH
Description
t
SFD
X-3
t
FDH
t
SFD
X-2
t
FDH
In this particular scenario, the developer must assert the
PKTEND at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet.
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 24
committed. The first packet is committed automatically when the
number of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte or word short packet being
committed manually using PKTEND. Note that there is at least
one IFCLK cycle timing between asserting PKTEND and
clocking of the last byte of the previous packet (causing the
packet to be committed automatically). Failing to adhere to this
timing results in the FX2 failing to send the one byte or word short
packet.
t
SFD
X-1
shows a scenario where two packets are being
t
FDH
20.83
Min
8.6
2.5
Figure 24
t
SFD
X
t
FDH
At least one IFCLK cycle
shows this scenario. X is the value
Max
13.5
200
t
SFD
1
>= t
t
FDH
WRH
CY7C64713
t
t
FAH
Unit
SPE
ns
ns
ns
ns
Page 41 of 55
t
[16]
PEH
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