CY8CTMG200-48LTXI Cypress Semiconductor Corp, CY8CTMG200-48LTXI Datasheet - Page 257

• Manufacturer Part Number: CY8CTMG200-48LTXI
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2955

21.3.65 CPU_SCR1
This register is used to convey the status and control of events related to internal resets and watchdog reset.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 137
Bit
7
4:3
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
CPU_SCR1: x,FEh
Access : POR
Bit Name
IRESS
SLIMO[1:0]
IRAMDIS
Name
in the System Resets chapter.
System Status and Control Register 1
IRESS
R : 0
7
6
Description
This bit is read only.
0
1
These bits set the frequency range for the IMO. Note When changing from the default setting, the
corresponding trim value must be loaded into the IMO_TR register for highest frequency accuracy.
SLIMO
00
01
10
11
0
1
Boot phase only executed once.
Boot phase occurred multiple times.
SRAM is initialized to 00h after POR, XRES, and WDR.
Addresses 03h - D7h of SRAM Page 0 are not modified by WDR.
5
CY8CTMG20x/ CY8CTST200
12
6
24
Reserved
4
SLIMO[1:0]
RW : 0
3
2
x,FEh
Register Definitions on
1
CPU_SCR1
IRAMDIS
x,FEh
RW : 0
0
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