CY8CTMG200-24LQXI Cypress Semiconductor Corp, CY8CTMG200-24LQXI Datasheet - Page 189
![IC MCU 32K FLASH 24UQFN](/photos/6/76/67623/cy8ctmg200-24lqxi_sml.jpg)
CY8CTMG200-24LQXI
Manufacturer Part Number
CY8CTMG200-24LQXI
Description
IC MCU 32K FLASH 24UQFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTMG200-24LQXI
Program Memory Type
FLASH (32 kB)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Applications
Touchscreen Controller
Core Processor
M8C
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
20
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Mounting Style
SMD/SMT
Program Memory Size
32 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2953
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8CTMG200-24LQXI
Manufacturer:
ST
Quantity:
367
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21.3.2
These registers enable or disable interrupts from individual GPIO pins.
The upper nibble of the PRT4IE register returns the last data bus value when read and must be masked off before using this
information. For additional information, refer to the
Bit
7:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
PRT0IE : 0,01h
PRT4IE : 0,11h
Access : POR
Bit Name
Interrupt Enables[7:0]
Name
Port Interrupt Enable Registers
PRTxIE
7
PRT1IE : 0,05h
6
Description
These bits enable the corresponding port pin interrupt. Only four LSB are used since this port has
four pins.
0
1
Port pin interrupt disabled for the corresponding pin.
Port pin interrupt enabled for the corresponding pin. Interrupt mode is determined by the
IOINT bit in the
5
Register Definitions on page 59
IO_CFG1
PRT2IE : 0,09h
Interrupt Enables[7:0]
4
RW : 00
register.
3
in the GPIO chapter.
PRT3IE : 0,0Dh
2
1
0,01h
0,01h
0
PRTxIE
189
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