CY8CTST200-48LTXI Cypress Semiconductor Corp, CY8CTST200-48LTXI Datasheet - Page 229
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CY8CTST200-48LTXI
Manufacturer Part Number
CY8CTST200-48LTXI
Description
IC MCU 32K FLASH 48-QFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-48LTXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
38
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-QFN
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2958
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8CTST200-48LTXI
Manufacturer:
MICREL
Quantity:
428
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21.3.41 I2C_BP
This register contains the base address value of the RAM data buffer and is read only.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
I2C Slave chapter.
Bit
4:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
I2C_BP
Access : POR
Bit Name
I2C Base Pointer[4:0]
Name
: 0,CBh
I
2
C Base Address Pointer Register
7
6
Description
In the EZI2C protocol, the first data byte after the slave address transaction in write mode is the base
address for subsequent reads and writes and it is transferred directly into this register. If the desired
transaction is a master write to the slave, subsequent bytes are written to the RAM buffer starting with
this address and auto incremented (see I2C_CP register). In case of a read, a Start or Restart must
be issued and the read location starts with this address and again subsequent read addresses are
auto incremented as pointed to by the I2C_CP register value.
The value of this register is modified only at the beginning of every I2C write transaction. The I2C
master must always supply a value for this register in the first byte of data after the slave’s address in
a given write transaction. If performing reads, the master need not set the value of this register. The
current value of this register is also used directly for reads.
5
0,CBh
4
3
I2C Base Pointer[4:0]
Register Definitions on page 122
0,D0h
R : 00
2
1
0,CBh
0
I2C_BP
in the
229
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