CY8CTST200-32LQXI Cypress Semiconductor Corp, CY8CTST200-32LQXI Datasheet - Page 264

• Manufacturer Part Number: CY8CTST200-32LQXI
• Description: IC MCU 32K FLASH 32UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-32LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 28
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2957

PMAx_RA
21.4.6
These registers are PSoC Memory Arbiter read address registers.
For additional information, refer to the
Bit
7:0
264
Individual Register Names and Addresses:
PMA0_RA : 1,3Ch
PMA4_RA : 1,40h
PMA8_RA : 1,4Ch
PMA12_RA : 1, 50h
Access : POR
Bit Name
1,3Ch
ReadAddress[7:0]
Name
PMAx_RA
PSoC Memory Arbiter Read Address Registers
7
PMA1_RA : 1,3Dh
PMA5_RA : 1,41h
PMA9_RA : 1,4Dh
PMA13_RA : 1,51h
6
Description
The value returned when this register is read depends on whether the PMA channel is being used by
the USB SIE or by the M8C. In the USB case, this register always returns the beginning SRAM
address for the PMA channel.
Register Definitions on page 171
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
5
PMA2_RA : 1,3Eh
PMA6_RA : 1,42h
PMA10_RA : 1,4Eh
PMA14_RA : 1,52h
4
Read Address[7:0]
RW : 00
in the Full-Speed USB chapter.
3
PMA3_RA : 1,3Fh
PMA7_RA : 1,43h
PMA15_RA : 1,53h
2
PMA11_RA : 1,4Fh
1
1,3Ch
0
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