EZ80L925048MOD Zilog, EZ80L925048MOD Datasheet - Page 14

• Manufacturer Part Number: EZ80L925048MOD
• Description: IC WEBSERVER 48MHZ 1MB MOD
• Manufacturer: Zilog

Specifications of EZ80L925048MOD

• Module/board Type: Development Module
• For Use With/related Products: eZ80L92
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3166; EZ80L925048MOD

I/O Connector
PS017005-0903
Pin #
1
2
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
Symbol
PB7
PB6
Figure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position
JP2 of the eZ80L92 Module. Table 2 describes the pins and their functions.
Figure 3. eZ80L92 Module I/O Connector Pin Configuration
Table 2. eZ80L92 Module I/O Connector Pin Identification*
Pull
Up/Down
GND_EXT
GND_EXT
V3.3_EXT
V3.3_EXT
HALT_SLP
RESET
FLASHWE
CS3
PB3
TCK
RTC_VDD
IICSCL
IICSDA
PB1
Signal
Direction
Bidirectional
Bidirectional
PB7
PB5
PC6
PC4
PC2
PC0
PD6
PD5
PD3
PD1
TDO
P R E L I M I N A R Y
JP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
HEADER 25X2
IDC50
DD
or GND, depending on their inactive levels, to reduce power
Comments
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
eZ80L92 Module Product Specification
PC7
PC5
PC3
PC1
PD7
WAIT
GND_EXT
NMI
PB6
PB4
PB2
PB0
PD4
PD2
PD0
TDI
TRIGOUT
TMS
GND_EXT
EZ80CLK
DIS_IRDA
GND_EXT
eZ80L925048MOD
Pin Description
8