EZ80L925048MODG Zilog, EZ80L925048MODG Datasheet - Page 20

• Manufacturer Part Number: EZ80L925048MODG
• Description: IC WEBSERVER 48MHZ 1MB MOD
• Manufacturer: Zilog

Specifications of EZ80L925048MODG

• Module/board Type: Development Module
• Processor To Be Evaluated: EZ80L92
• Interface Type: JTAG
• For Use With/related Products: eZ80L92
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4670; EZ80L925048MODG; Q2608719

Memory
PS017005-0903
EMAC Ports
EMAC Wait States
Wait States
the module is required for this function. In this case, the PD6 pin is not available
for GPIO on the I/O connector.
Chip Select CS3 is used for selecting the EMAC via I/O decoding. The I/O base
address is user-selectable. The EMAC is connected as an 8- or 16-bit device with
8-word-wide I/O registers:
The CS8900A EMAC should be operated in Intel bus mode so that the setup and
hold times for the I/O access are met. For 48 MHz operation, first set CS3_BMC (I/
O address
cycle) and then CS3_CTL (I/O Address
20.8 ns CPU Clock cycle time, the Read and
The eZ80L92 Module offers SRAM and Flash memories and the wait states that
support memory operations, as described in this section.
To ensure that valid data is read from or written to slower memories, a number of
wait states must be inserted into the memory or I/O access operations by the pro-
cessor. The number of wait states that are required should be added by program-
ming the chip select control registers. To calculate the minimum number of wait
states required, refer to Table 4.
Table 4. Chip Frequency to Wait State Cycle Time Calculation
2 x 4 x 20.8 ns–16 ns (for capacitive and chip delays) = 150 ns
0xF3h
) to
84h
MHz
12
20
24
36
40
48
P R E L I M I N A R Y
(Intel bus mode with four system clock cycles per bus
Cycle Time
83.3 ns
50.0 ns
41.7 ns
27.8 ns
25.0 ns
20.8 ns
0xB3
eZ80L92 Module Product Specification
) to
Write
18h
access time is:
(0 wait states for I/O). For a
Onboard Component Description
eZ80L925048MOD
14