AT94K40AL-25DQC Atmel, AT94K40AL-25DQC Datasheet - Page 101
![IC FPSLIC 40K GATE 25MHZ 208PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT94K40AL-25DQC
Manufacturer Part Number
AT94K40AL-25DQC
Description
IC FPSLIC 40K GATE 25MHZ 208PQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K40AL-25DQC
Core Type
8-bit AVR
Speed
18MHz
Interface
I²C, UART
Program Sram Bytes
20K-32K
Fpga Sram
18kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
2304
Fpga Gates
40K
Fpga Registers
2862
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
208-MQFP, 208-PQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT94K40AL-25DQC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.26
Figure 4-31. Timer/Counter1 Block Diagram
1138I–FPSLI–1/08
Timer/Counter1
REGISTER (TIMSK)
15
15
15
15
TIMER INT. MASK
TIMER/COUNTER1 OUTPUT COMPARE REGISTER A
T/C1 OVER-
T/C1 INPUT CAPTURE REGISTER (ICR1)
FLOW IRQ
TIMER/COUNTER1 (TCNT1)
16 BIT COMPARATOR
Figure 4-31
The 16-bit Timer/Counter1 can select the clock source from CK, prescaled CK, or an external
pin. In addition it can be stopped as described in section
TCCR1B” on page
are found in the Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the
Timer/Counter1 Control Registers – TCCR1A and TCCR1B. The interrupt enable/disable set-
tings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register – TIMSK.
When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscilla-
tor frequency of the CPU. To assure proper sampling of the external clock, the minimum time
between two external clock transitions must be at least one internal CPU clock period. The
external clock signal is sampled on the rising edge of the internal CPU clock.
The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the
lower prescaling opportunities. Similarly, the high-prescaling opportunities makes the
T/C1 COMPARE
8
MATCHA IRQ
8
8
8
7
7
7
7
TIMER INT. FLAG
REGISTER (TIFR)
shows the block diagram for Timer/Counter1.
T/C1 COMPARE
MATCHB IRQ
104. The different status flags (overflow, compare match and capture event)
CAPTURE
TRIGGER
0
0
0
0
REGISTER A (TCCR1A)
15
15
TIMER/COUNTER1 OUTPUT COMPARE REGISTER B
T/C CLEAR
T/C CLOCK SOURCE
UP/DOWN
T/C1 CONTROL
CAPTURE IRQ
T/C1 INPUT
16 BIT COMPARATOR
CONTROL
AT94KAL Series FPSLIC
LOGIC
8
8
7
7
REGISTER B (TCCR1B)
T/C1 CONTROL
“Timer/Counter1 Control Register B –
0
0
SPECIAL FUNCTIONS
IO REGISTER (SFIOR)
T1
CK
101
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