XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 192
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
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Company:
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
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- Download datasheet (14Mb)
Chapter 5: Configurable Logic Blocks (CLBs)
192
Figure 5-17
single LUT.
X-Ref Target - Figure 5-17
As mentioned earlier, an additional output (MC31) and a dedicated connection between
shift registers allows connecting the last bit of one shift register to the first bit of the next,
without using the LUT O6 output. Longer shift registers can be built with dynamic access
to any bit in the chain. The shift register chaining and the F7AMUX, F7BMUX, and F8MUX
multiplexers allow up to a 128-bit shift register with addressable access to be implemented
in one SLICEM.
configurations that can occupy one SLICEM.
X-Ref Target - Figure 5-18
SHIFTIN (D)
A[5:0]
CLK
WE
shows two 16-bit shift registers. The example shown can be implemented in a
Figure 5-18
Figure 5-17: Dual 16-bit Shift Register Configuration
SHIFTIN1 (AX)
SHIFTIN2 (AI)
Figure 5-18: 64-bit Shift Register Configuration
(WE/CE)
(CLK)
A[3:0]
CLK
www.xilinx.com
CE
through
5
5
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
Figure 5-20
SRL32
SRL32
MC31
MC31
O6
O6
4
4
DI1
A[5:2]
CLK
WE
DI2
A[5:2]
CLK
WE
illustrate various example shift register
F7AMUX
SRL16
SRL16
A5 (AX)
MC31
SHIFTOUT (Q63)
O5
O6
UG190_5_17_050506
Virtex-5 FPGA User Guide
D Q
UG190 (v5.3) May 17, 2010
(MC31)
(Optional)
(AQ)
UG190_5_18_050506
Output (Q)
Registered
Output
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