XC4062XL-1BG560I Xilinx Inc, XC4062XL-1BG560I Datasheet - Page 59
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XC4062XL-1BG560I
Manufacturer Part Number
XC4062XL-1BG560I
Description
IC FPGA I-TEMP 3.3V 1SPD 560MBGA
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4062XL-1BG560I
Number Of Logic Elements/cells
5472
Number Of Labs/clbs
2304
Total Ram Bits
73728
Number Of I /o
384
Number Of Gates
62000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
560-LBGA, Metal
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Figure 55: Master Parallel Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
(output)
(output)
(output)
(output)
A0-A17
D0-D7
DOUT
RCLK
CCLK
RCLK
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
Low until Vcc is valid.
R
Delay to Address valid
Data setup time
Data hold time
Product Obsolete or Under Obsolescence
Description
XC4000E and XC4000X Series Field Programmable Gate Arrays
Address for Byte n
1
2
3
Symbol
7 CCLKs
T
T
T
DRC
RCD
RAC
2 T
Byte
DRC
Min
60
0
0
Byte n - 1
D6
Address for Byte n + 1
1 T
3 T
CCLK
RAC
Max
RCD
200
D7
Units
ns
ns
ns
X6078
6-63
6