XC4013XL-1PQ240I Xilinx Inc, XC4013XL-1PQ240I Datasheet - Page 10

• Manufacturer Part Number: XC4013XL-1PQ240I
• Description: IC FPGA I-TEMP 3.3V 1SPD 240PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4013XL-1PQ240I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 192
• Number Of Gates: 13000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL standards.
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted
Global Low Skew Clock, Set-Up and Hold
6-82
Input Setup and Hold Times
No Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
Partial Delay
Global Low Skew Clock and IFF
Global Low Skew Clock and FCL
Full Delay
Global Low Skew Clock and IFF
IFF = Input Flip-Flop or Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
Description
T
T
T
Symbol
PSN
PSD
PSP
/T
/T
/T
PHN
PHP
PHD
Speed Grade
XC4013XL*
XC4036XL*
XC4062XL*
XC4013XL*
XC4036XL*
XC4062XL*
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
XC4002XL
XC4005XL
XC4010XL
XC4020XL
XC4028XL
XC4044XL
XC4052XL
XC4085XL
XC4002XL
XC4005XL
XC4010XL
XC4020XL
XC4028XL
XC4044XL
XC4052XL
XC4085XL
Device
10. 5 / 0.0
11.1 / 0.0
11.9 / 1.0
12.3 / 1.0
13.1 / 1.0
11.9 / 1.0
12.9 / 1.2
10.6 / 0.0
11.2 / 0.0
12.7 / 0.0
2.5 / 1.5
1.2 / 2.6
1.2 / 3.0
1.2 / 3.2
1.2 / 3.7
1.2 / 4.4
1.2 / 5.5
1.2 / 5.8
1.2 / 7.1
1.2 / 7.0
1.2 / 9.4
8.4 / 0.0
6.1 / 1.0
6.4 / 1.0
6.7 / 1.2
6.8 / 0.0
8.8 / 0.0
9.0 / 0.0
6.4 / 0.0
8.8 / 0.0
9.3 / 0.0
6.6 / 0.0
6.8 / 0.0
Min
-3
DS005 (v. 1.8 October 18, 1999 - Product Specification
10.3 / 1.0
10.7 / 1.0
11.4 / 1.0
10.3 / 1.0
11.2 / 1.2
11.0 / 0.0
2.2 / 1.3
1.1 / 2.2
1.1 / 2.6
1.1 / 2.8
1.1 / 3.2
1.1 / 3.8
1.1 / 4.8
1.1 / 5.0
1.1 / 6.2
1.1 / 6.1
1.1 / 8.2
7.3 / 0.0
9.1 / 0.0
9.7 / 0.0
5.3 / 1.0
5.6 / 1.0
5.8 / 1.2
6.0 / 0.0
7.6 / 0.0
7.8 / 0.0
6.0 / 0.0
7.6 / 0.0
8.1 / 0.0
6.2 / 0.0
9.2 / 0.0
9.7 / 0.0
6.4 / 0.0
Min
-2
1.9 / 1.2
0.9 / 2.0
0.9 / 2.3
0.9 / 2.4
0.9 / 2.8
0.9 / 3.3
0.9 / 4.1
0.9 / 4.4
0.9 / 5.4
0.9 / 5.3
0.9 / 7.1
6.3 / 0.0
7.9 / 0.0
8.4 / 0.0
4.6 / 1.0
9.0 / 1.0
9.3 / 1.0
4.8 / 1.0
9.9 / 1.0
9.0 / 1.0
5.1 / 1.2
9.8 / 1.2
5.2 / 0.0
6.6 / 0.0
6.8 / 0.0
5.6 / 0.0
6.6 / 0.0
7.0 / 0.0
5.8 / 0.0
8.0 / 0.0
8.4 / 0.0
6.0 / 0.0
9.6 / 0.0
Min
-1
1.7 / 1.0
0.8 / 1.7
0.8 / 2.0
0.8 / 2.1
0.8 / 2.4
0.8 / 2.9
0.8 / 3.6
0.8 / 3.8
0.8 / 4.7
0.8 / 4.6
0.8 / 6.2
5.5 / 0.0
6.9 / 0.0
7.3 / 0.0
4.0 / 1.0
7.8 / 1.0
8.1 / 1.0
4.2 / 1.0
8.6 / 1.0
7.8 / 1.0
4.4 / 1.2
8.5 / 1.2
4.5 / 0.0
5.6 / 0.0
5.8 / 0.0
4.8 / 0.0
6.2 / 0.0
6.4 / 0.0
5.3 / 0.0
6.8 / 0.0
7.0 / 0.0
5.5 / 0.0
8.4 / 0.0
Min
-09
All devices are 100%
0.8 / 2.1
0.8 / 3.6
0.8 / 4.6
3.7 / 0.5
4.8 / 0.0
5.3 / 0.0
5.5 / 0.0
4.0/ 0.8
4.2/ 1.0
Min
-08
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R