XC4013XL-1HT176I Xilinx Inc, XC4013XL-1HT176I Datasheet - Page 40
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XC4013XL-1HT176I
Manufacturer Part Number
XC4013XL-1HT176I
Description
IC FPGA I 3.3V 1SPD 176HTQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4013XL-1HT176I
Number Of Logic Elements/cells
1368
Number Of Labs/clbs
576
Total Ram Bits
18432
Number Of I /o
145
Number Of Gates
13000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
176-LQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC4000E and XC4000X Series Field Programmable Gate Arrays
Instruction Set
The XC4000 Series boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only M0 and M2 mode pins contribute only the In bit
to the boundary scan I/O data register, while the out-
put-only M1 pin contributes all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in XDE or
Epic), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in
The device-specific pinout tables for the XC4000 Series
include the boundary scan locations for each IOB pin.
6-44
Figure 41: XC4000 Series Boundary Scan Logic
Table
TDI
17.
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
Product Obsolete or Under Obsolescence
INSTRUCTION REGISTER
IOB
REGISTER
BYPASS
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
Figure
TDO
42.
IOB.Q
IOB.T
IOB.T
IOB.I
IOB.I
CAPTURE
SHIFT/
DATAOUT
BSDL (Boundary Scan Description Language) files for
XC4000 Series devices are available on the Xilinx FTP site.
Including Boundary Scan in a Schematic
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the sche-
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
tions after configuration.
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in
Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.
DATA IN
CLOCK DATA
1
0
1
0
1
0
1
0
1
0
REGISTER
D
D
D
D
D
Q
Q
Q
Q
Q
UPDATE
Figure
D
D
D
D
D
LE
LE
LE
LE
LE
sd
sd
sd
sd
sd
Q
Q
Q
Q
Q
43.
0
1
1
0
1
0
0
1
1
0
May 14, 1999 (Version 1.6)
EXTEST
X9016
R