XC4010XL-09TQ144C Xilinx Inc, XC4010XL-09TQ144C Datasheet - Page 9

• Manufacturer Part Number: XC4010XL-09TQ144C
• Description: IC FPGA C-TEMP 3.3V 144-TQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4010XL-09TQ144C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 113
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• Case: TQFP144
• Dc: 01+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Output Flip-Flop, Clock to Out, BUFGE #s 1, 2, 5, and 6
Output Flip-Flop, Clock to Out, BUFGE #s 3, 4, 7, and 8
DS005 (v. 1.8 October 18, 1999 - Product Specification
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 1, 2, 5, and 6.
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
Output timing is measured at ~50% V
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 3, 4, 7, and 8.
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
Output timing is measured at ~50% V
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Description
Description
R
CC
threshold with 50 pF external capacitive load. For different loads, see Figure 60.
XC4000E and XC4000X Series Field Programmable Gate Arrays
T
T
Symbol
Symbol
ICKEOF
ICKEOF
CC
threshold with 50 pF external capacitive load. For different loads, see Figure 60.
Speed Grade
Speed Grade
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
Device
Device
Min
Min
1.3
1.5
1.6
1.6
1.7
1.7
1.8
1.9
2.0
2.0
2.2
1.0
1.2
1.2
1.3
1.3
1.2
1.2
1.1
1.2
1.2
1.3
All
All
Max
10.1
10.5
10.9
11.8
Max
10.8
7.8
8.1
8.5
8.8
9.1
9.4
9.7
6.6
6.9
7.2
7.4
7.6
7.8
8.1
8.5
9.0
9.9
-3
-3
Max
10.3
Max
6.8
7.1
7.4
7.6
7.9
8.2
8.5
8.8
9.1
9.5
5.7
6.1
6.2
6.4
6.5
6.7
7.0
7.3
7.8
8.6
9.4
-2
-2
Max
Max
5.9
6.5
6.6
6.7
7.2
7.2
7.5
7.8
8.1
8.6
9.3
5.1
5.5
5.5
5.6
5.9
5.9
6.1
6.4
6.8
7.5
8.5
-1
-1
Max
Max
-09
5.3
6.1
6.3
6.4
6.8
6.9
7.2
7.3
7.9
8.1
8.8
-09
4.8
5.2
5.3
5.3
5.6
5.6
5.8
6.0
6.6
7.0
7.9
Max
Max
-08
5.7
6.4
7.3
-08
4.8
5.2
6.3
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-81
6