XC4003E-4PQ100I Xilinx Inc, XC4003E-4PQ100I Datasheet - Page 61
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XC4003E-4PQ100I
Manufacturer Part Number
XC4003E-4PQ100I
Description
IC FPGA I-TEMP 5V 4-SPD 100-PQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4003E-4PQ100I
Number Of Logic Elements/cells
238
Number Of Labs/clbs
100
Total Ram Bits
3200
Number Of I /o
77
Number Of Gates
3000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-BQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
CCLK
INIT
CCLK
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
not require such a response.
additional CCLK pulses are clearly required after the last byte has been loaded.
RDY/BUSY
R
DOUT
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
Product Obsolete or Under Obsolescence
Description
BYTE
0
XC4000E and XC4000X Series Field Programmable Gate Arrays
0
1
Symbol
T
T
T
T
F
T
CCH
CCL
DC
CD
CC
IC
2
BYTE 0 OUT
3
4
Min
60
50
60
5
0
5
BYTE
1
6
Max
8
7
BYTE 1 OUT
0
Units
MHz
1
ns
ns
ns
ns
s
X6096
6-65
6