XC5202-6PQ100C Xilinx Inc, XC5202-6PQ100C Datasheet - Page 28

• Manufacturer Part Number: XC5202-6PQ100C
• Description: IC FPGA 64 CLB'S 100-PQFP
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5202-6PQ100C

• Number Of Logic Elements/cells: 256
• Number Of Labs/clbs: 64
• Number Of I /o: 81
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Case: QFP100
• Dc: 99+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1132

XC5200 Series Field Programmable Gate Arrays
Configuration
The length counter begins counting immediately upon entry
into the configuration state. In slave-mode operation it is
important to wait at least two cycles of the internal 1-MHz
clock oscillator after INIT is recognized before toggling
CCLK and feeding the serial bitstream. Configuration will
not begin until the internal configuration logic reset is
released, which happens two cycles after INIT goes High.
A master device’s configuration is delayed from 32 to 256
by the master device.
The 0010 preamble code, included for all modes except
Express mode, indicates that the following 24 bits repre-
sent the length count. The length count is the total number
of configuration clocks needed to load the complete config-
uration data.
required to complete the configuration process, as dis-
cussed below.) After the preamble and the length count
have been passed through to all devices in the daisy chain,
DOUT is held High to prevent frame start bits from reaching
any daisy-chained devices. In Express mode, the length
count bits are ignored, and DOUT is held Low, to disable
the next device in the pseudo daisy chain.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configu-
ration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configura-
tion frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device. In Express mode, when the first
device is fully programmed, DOUT goes High to enable the
next device in the chain.
Delaying Configuration After Power-Up
To delay master mode configuration after power-up, pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of master mode configuration
causes the FPGA to wait after completing the configuration
memory clear operation. When INIT is no longer held Low
externally, the device determines its configuration mode by
capturing its mode pins, and is ready to start the configura-
tion process. A master device waits up to an additional 250
have seen that INIT is High.
7-110
s to ensure proper operation with any slave devices driven
s to make sure that any slaves in the optional daisy chain
(Four additional configuration clocks are
Product Obsolete or Under Obsolescence
Figure
12.)
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user-system. Start-up must make sure that
the user-logic ‘wakes up’ gracefully, that the outputs
become active without causing contention with the configu-
ration signals, and that the internal flip-flops are released
from the global Reset at the right time.
Figure 25
ilies in detail. Express mode configuration always uses
either CCLK_SYNC or UCLK_SYNC timing, the other con-
figuration modes can use any of the four timing sequences.
To access the internal start-up signals, place the STARTUP
library symbol.
Start-up Timing
Different FPGA families have different start-up sequences.
The XC2000 family goes through a fixed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
The XC3000A family offers some flexibility. DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000/XC5200 Series offers additional flexibility.
The three events — DONE going High, the internal Reset
being de-activated, and the user I/O going active — can all
occur in any arbitrary sequence. Each of them can occur
one CCLK period before or after, or simultaneous with, any
of the others. This relative timing is selected by means of
software options in the bitstream generation software.
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention when the I/Os become active
one clock later. Reset is then released another clock period
later to make sure that user-operation starts from stable
internal conditions. This is the most common sequence,
shown with heavy lines in
modify it to meet particular requirements.
Normally, the start-up sequence is controlled by the internal
device oscillator output (CCLK), which is asynchronous to
the system clock.
XC4000/XC5200 Series offers another start-up clocking
option, UCLK_NOSYNC.
above need not be triggered by CCLK. They can, as a con-
figuration option, be triggered by a user clock. This means
that the device can wake up in synchronism with the user
system.
describes start-up timing for the three Xilinx fam-
November 5, 1998 (Version 5.2)
Figure
The three events described
25, but the designer can
R