XC3164A-3TQ144C Xilinx Inc, XC3164A-3TQ144C Datasheet - Page 29

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XC3164A-3TQ144C

Manufacturer Part Number
XC3164A-3TQ144C
Description
IC FPGA 224 CLB'S 144-TQFP
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet

Specifications of XC3164A-3TQ144C

Number Of Labs/clbs
224
Total Ram Bits
46064
Number Of I /o
120
Number Of Gates
4500
Voltage - Supply
4.25 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1084

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Quantity:
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Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
Figure 29: Slave Serial Mode Circuit Diagram
November 9, 1998 (Version 3.1)
R
RESET
Product Obsolete or Under Obsolescence
Computer
Micro
Port
I/O
STRB
D0
D1
D2
D3
D4
D5
D6
D7
+5 V
+5 V
XC3000 Series Field Programmable Gate Arrays
CCLK
DIN
INIT
RESET
M0
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
D/P
*
M1
FPGA
PWRDWN
I/O Pins
Other
DOUT
HDC
LDC
M2
5 k
General-
Purpose
User I/O
Pins
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
Activated, a
5-k Resistor is
Required in
Series with M1
If Readback is
X5993
7-31
7

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