XC2018-70PC68C Xilinx Inc, XC2018-70PC68C Datasheet - Page 8

• Manufacturer Part Number: XC2018-70PC68C
• Description: IC LOGIC CL ARRAY 1800GAT 68PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC68C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 58
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1003

XC2000 Logic Cell Array Families
can connect an interconnect segment to other segments
to form a network. Figure 7a shows the general intercon-
nect used to route a signal from one logic block to three
other logic blocks. As shown, combinations of closed
switches in a switch matrix allow multiple branches for
each network. The inputs of the logic or I/O blocks are
multiplexers that can be programmed with configuration
bits to select an input network from the adjacent intercon-
nect segments. Since the switch connections to block
inputs are unidirectional (as are block outputs) they are
usable only for input connection. The development sys-
tem software provides automatic routing of these intercon-
nections. Interactive routing is also available for design
optimization. This is accomplished by selecting a network
and then toggling the states of the interconnect points by
selecting them with the “mouse”. In this mode, the connec-
tions through the switch matrix may be established by
selecting pairs of matrix pins. The switching matrix combi-
nations are indicated in Figure 7b.
Special buffers within the interconnect area provide peri-
odic signal isolation and restoration for higher general
Figure 7b. Routing and Switch Matrix Connections
d
a
X
Y
5 Vertical General
Purpose Interconnects
Between Switch Matrics
Long Lines
2 Vertical
Programmable
Interconnect Points
(Do Not Use More Than
One Per Input Pin)
b
c
k
Global
Net
2-192
a
d
Figure 7a. General-Purpose Interconnect
4 Horizontal
General Purpose
Interconnect
Horizontal
Long Line
Switch
Matrices
C
B
K
D
CLB
CLB
CLB
Available Programmable
Switch Matrix Interconnections
of General Interconnect
Segments by Pin
A
X
Y
8
7
8
7
8
7
8
7
1
6
1
6
1
6
1
6
Switch
Switch
Matrix
Matrix
2
5
2
5
2
5
2
5
3
4
3
4
3
4
3
4
8
7
8
7
8
7
8
7
See Fig. 7b
1
6
1
6
1
6
1
6
X3175
2
5
2
5
2
5
2
5
3
4
3
4
3
4
3
4
CLB
CLB
CLB
X5401