XC4003-6PC84C Xilinx Inc, XC4003-6PC84C Datasheet - Page 2

• Manufacturer Part Number: XC4003-6PC84C
• Description: IC LOGIC CL ARRAY 3000GAT 84 PLC
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4003-6PC84C

• Number Of Logic Elements/cells: 238
• Number Of Labs/clbs: 100
• Total Ram Bits: 3200
• Number Of I /o: 61
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1066

IOB has more versatile clocking polarity options.
IOB has programmable input set-up time:
IOB has Longline access through its own TBUF.
Outputs are n-channel only, lower V
XC4000, XC4000A, XC4000H Logic Cell Array Families
XC4000 Compared to XC3000A
For those readers already familiar with the XC3000A
family of Xilinx Field Programmable Gate Arrays, here is a
concise list of the major new features in the XC4000 family.
CLB has two independent 4-input function generators.
CLB has very fast arithmetic carry capability.
CLB function generator look-up table can also be used as
CLB flip-flops have asynchronous set or reset.
CLB has four outputs, two flip-flops, two combinatorial.
CLB connections symmetrically located on all four edges.
XC4000 outputs can be paired to double sink current to
IEEE 1149.1- type boundary scan is supported in the I/O.
Wide decoders on all four edges of the LCA device.
Table 2. Three Generations of Xilinx Field-Programmable Gate Array Families
A third function generator combines the outputs of the
two other function generators with a ninth input.
All function inputs are swappable, all have full access;
none are mutually exclusive.
high-speed RAM.
long to avoid potential hold time problems,
short to improve performance.
24 mA. XC4000A and XC4000H outputs can each
sink 24 mA, can be paired for 48 mA sink current.
Number of flip-flops
Max number of user I/O
Max number of RAM bits
Function generators per CLB
Number of logic inputs per CLB
Number of logic outputs per CLB
Number of low-skew global nets
Dedicated decoders
Fast carry logic
Internal 3-state drivers
Output slew-rate control
Power-down option
Crystal oscillator circuit
Parameter
OH
increases speed.
XC4025
32,768
2,560
256
yes
yes
yes
yes
no
no
3
9
4
8
2-8
Increased number of interconnect resources.
All CLB inputs and outputs have access to most inter-
Switch Matrices are simplified to increase speed.
Eight global nets can be used for clocking or distributing
TBUF output configuration is more versatile and 3-state
Program is single-function input pin,overrides everything.
INIT pin also acts as Configuration Error output.
Peripheral Synchronous Mode (8 bit) has been added.
Peripheral Asynchronous Mode has improved hand-
Start-up can be synchronized to any user clock (this is a
No Powerdown, but instead a Global 3-state input that
No on-chip crystal oscillator amplifier.
Configuration Bit Stream includes CRC error checking.
Configuration Clock can be increased to >8 MHz.
Configuration Clock is fully static, no constraint on the
Readback either ignores flip-flop content (avoids need for
Readback has same polarity as Configuration and can be
connect lines.
logic signals.
control less confined.
shake.
configuration option).
does not reset any flip-flops.
maximum Low time.
masking) or it takes a snapshot of all flip-flops at the
start of Readback.
aborted.
XC3195A
1,320
176
yes
yes
yes
yes
no
no
0
2
5
2
2
XC2018
174
yes
yes
74
no
no
no
no
0
2
4
2
2