AT40K40LV-3DQC Atmel, AT40K40LV-3DQC Datasheet - Page 9

• Manufacturer Part Number: AT40K40LV-3DQC
• Description: IC FPGA 3.3V 2304 CELL 208-PQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K40LV-3DQC

• Number Of Logic Elements/cells: 2304
• Total Ram Bits: 18432
• Number Of I /o: 161
• Number Of Gates: 50000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -

RAM
32 x 4 Dual-Ported RAM blocks are dispersed throughout
the array as shown in Figure 7. A four-bit Input Data Bus
connects to four horizontal local buses distributed over four
sector rows (plane 1). A four-bit Output Data Bus connects
to four horizontal local buses distributed over four sector
rows (plane 2). A five-bit Input-Address Bus connects to
five vertical express buses in same column. A five-bit Out-
put-Address Bus connects to five vertical express buses in
same column. WAddr (Write Address) and RAddr (Read
Address) alternate positions in horizontally aligned RAM
Figure 7. RAM Connections (One Ram Block)
blocks. For the left-most RAM blocks, RAddr is on the left
and WAddr is on the right. For the right-most RAM blocks,
WAddr is on the left and RAddr is tied off. For single-ported
RAM, WAddr is the READ/WRITE address port and Din is
the (bi-directional) data port. Right-most RAM blocks can
be used only for single-ported memories. /WE & /OE con-
nect to the vertical express buses in the same column.
WAddr, RAddr, /WE and /OE connect to express buses
that are full length at array edge.
AT40K
CL
CL
CL
CL
WAdd
W
O
CL
Di
32X4
Dou
RAdd
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