XC5VSX240T-1FFG1738C Xilinx Inc, XC5VSX240T-1FFG1738C Datasheet - Page 5
![no-image](/images/no-image-200.jpg)
XC5VSX240T-1FFG1738C
Manufacturer Part Number
XC5VSX240T-1FFG1738C
Description
IC FPGA VIRTEX 5 40K 1738FFGBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheet
1.XC5VLX30-1FFG324C.pdf
(13 pages)
Specifications of XC5VSX240T-1FFG1738C
Number Of Logic Elements/cells
239616
Number Of Labs/clbs
18720
Total Ram Bits
19021824
Number Of I /o
960
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX240T-1FFG1738C
Manufacturer:
XILINX
Quantity:
128
Company:
Part Number:
XC5VSX240T-1FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC5VSX240T-1FFG1738CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
RocketIO GTP Transceivers (LXT/SXT only)
•
•
•
•
•
•
•
•
•
•
•
•
•
RocketIO GTX Transceivers (TXT/FXT only)
•
•
•
•
•
•
•
•
•
•
•
•
•
DS100 (v5.0) February 6, 2009
Product Specification
Full-duplex serial transceiver capable of 100 Mb/s to
3.75 Gb/s baud rates
8B/10B, user-defined FPGA logic, or no encoding
options
Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
Programmable termination and voltage swing
Programmable equalization for the receiver
Receiver signal detect and loss of signal indicator
User dynamic reconfiguration using secondary
configuration bus
Out of Band (OOB) support for Serial ATA (SATA)
Electrical idle, beaconing, receiver detection, and PCI
Express and SATA spread-spectrum clocking support
Less than 100 mW typical power consumption
Built-in PRBS Generators and Checkers
Full-duplex serial transceiver capable of 150 Mb/s to
6.5 Gb/s baud rates
8B/10B encoding and programmable gearbox to
support 64B/66B and 64B/67B encoding, user-defined
FPGA logic, or no encoding options
Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
Programmable termination and voltage swing
Programmable continuous time equalization for the
receiver
Programmable decision feedback equalization for the
receiver
Receiver signal detect and loss of signal indicator
User dynamic reconfiguration using secondary
configuration bus
OOB support (SATA)
Electrical idle, beaconing, receiver detection, and
PCI Express spread-spectrum clocking support
Low-power operation at all line rates
R
www.xilinx.com
PowerPC 440 RISC Cores (FXT only)
•
•
•
Embedded PowerPC 440 (PPC440) cores
−
−
−
−
−
−
−
−
Integrated crossbar for enhanced system performance
−
−
−
−
Auxiliary Processor Unit (APU) Interface and Controller
−
−
−
−
Up to 550 MHz operation
Greater than 1000 DMIPS per core
Seven-stage pipeline
Multiple instructions per cycle
Out-of-order execution
32 Kbyte, 64-way set associative level 1 instruction
cache
32 Kbyte, 64-way set associative level 1 data cache
Book E compliant
128-bit Processor Local Buses (PLBs)
Integrated scatter/gather DMA controllers
Dedicated interface for connection to DDR2 memory
controller
Auto-synchronization for non-integer PLB-to-CPU clock
ratios
Direct connection from PPC440 embedded block to
FPGA fabric-based coprocessors
128-bit wide pipelined APU Load/Store
Support of autonomous instructions: no pipeline stalls
Programmable decode for custom instructions
Virtex-5 Family Overview
5