XC5VLX220T-2FFG1738C Xilinx Inc, XC5VLX220T-2FFG1738C Datasheet - Page 91
XC5VLX220T-2FFG1738C
Manufacturer Part Number
XC5VLX220T-2FFG1738C
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-2FFG1738C
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7815168
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Input muxes select the reference and feedback clocks from either the IBUFG, BUFG, IBUF,
PLL outputs, or one of the DCMs. Each clock input has a programmable counter D. The
Phase-Frequency Detector (PFD) compares both phase and frequency of the input
(reference) clock and the feedback clock. Only the rising edges are considered because as
long as a minimum High/Low pulse is maintained, the duty cycle is not important. The
PFD is used to generate a signal proportional to the phase and frequency between the two
clocks. This signal drives the Charge Pump (CP) and Loop Filter (LF) to generate a
reference voltage to the VCO. The PFD produces an up or down signal to the charge pump
and loop filter to determine whether the VCO should operate at a higher or lower
frequency. When VCO operates at too high of a frequency, the PFD activates a down signal,
causing the control voltage to be reduced decreasing the VCO operating frequency. When
the VCO operates at too low of a frequency, an up signal will increase voltage. The VCO
produces eight output phases. Each output phase can be selected as the reference clock to
the output counters
given customer design. A special counter, M, is also provided. This counter controls the
feedback clock of the PLL allowing a wide range of frequency synthesis.
X-Ref Target - Figure 3-3
General
CLKIN1
CLKIN2
Routing
CLKFB
Switch
Circuit
Clock
(Figure
D
Figure 3-3: Detailed PLL Block Diagram
www.xilinx.com
3-3.) Each counter can be independently programmed for a
PFD
Lock Detect
Lock Monitor
CLKFBOUT
CP
VCO feedback phase
selection for negative
phase-shift affecting
all outputs
M
LF
Lock
VCO
8
8-phase
taps
UG190_c3_03_022709
Introduction
O0
O1
O2
O3
O4
O5
91
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