XC5VLX110T-3FF1738C Xilinx Inc, XC5VLX110T-3FF1738C Datasheet - Page 116
![IC FPGA VIRTEX-5 110K 1738FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-3FF1738C
Manufacturer Part Number
XC5VLX110T-3FF1738C
Description
IC FPGA VIRTEX-5 110K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-3FF1738C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-3FF1738C
Manufacturer:
XILINX
Quantity:
250
Company:
Part Number:
XC5VLX110T-3FF1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 4: Block RAM
116
X-Ref Target - Figure 4-1
Table 4-2: True Dual-Port Names and Descriptions
DI[A|B]
DIP[A|B]
ADDR[A|B]
WE[A|B]
EN[A|B]
SSR[A|B]
CLK[A|B]
DO[A|B]
DOP[A|B]
REGCE[A|B]
CASCADEINLAT[A|B]
Port Name
(1)
(1)
CASCADEOUTREGA
Figure 4-1: True Dual-Port Data Flows
CASCADEOUTLATA
www.xilinx.com
CASCADEINREGA
CASCADEINLATA
DIA
DIPA
ADDRA
WEA
ENA
SSRA
REGCEA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
REGCEB
Data Input Bus
Data Input Parity Bus, can be used for additional data inputs
Address Bus
Byte-wide Write Enable
When inactive no data is written to the block RAM and the
output bus remains in its previous state
Synchronous Set/Reset for either latch or register modes
Clock Input
Data Output Bus
Data Output Parity Bus, can be used for additional data
outputs
Output Register Enable
Cascade input pin for 64K x 1 mode when optional output
registers are not enabled
CLKA
CLKB
36-Kbit Block RAM
Memory
Port A
Port B
36 Kb
Array
CASCADEOUTLATB
CASCADEOUTREGB
CASCADEINLATB
CASCADEINREGB
DOPB
DOPA
DOB
DOA
Description
ug0190_4_01_032106
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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