XC5VLX110T-2FF1738I Xilinx Inc, XC5VLX110T-2FF1738I Datasheet - Page 129
![IC FPGA VIRTEX-5 110K 1738FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-2FF1738I
Manufacturer Part Number
XC5VLX110T-2FF1738I
Description
IC FPGA VIRTEX-5 110K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-2FF1738I
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1738-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-2FF1738I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Content Initialization - INITP_xx
Output Latches Initialization - INIT (INIT_A or INIT_B)
Table 4-9: Block RAM Initialization Attributes
INITP_xx attributes define the initial contents of the memory cells corresponding to
DIP/DOP buses (parity bits). By default these memory cells are also initialized to all zeros.
The initialization attributes represent the memory contents of the parity bits. The eight
initialization attributes are INITP_00 through INITP_07 for the RAMB18. The 16
initialization attributes are INITP_00 through INITP_0F for the RAMB36. Each INITP_xx is
a 64-digit hex-encoded bit vector with a regular INIT_xx attribute behavior. The same
formula can be used to calculate the bit positions initialized by a particular INITP_xx
attribute.
The INIT (single-port) or INIT_A and INIT_B (dual-port) attributes define the output
latches or output register values after configuration. The width of the INIT (INIT_A and
INIT_B) attribute is the port width, as shown in
encoded bit vectors, and the default value is 0. In cascade mode, both the upper and lower
block RAM should be initialized to the same value.
Attribute
INIT_0E
INIT_00
INIT_01
INIT_02
INIT_0F
INIT_10
INIT_1F
INIT_20
INIT_2F
INIT_30
INIT_3F
INIT_7F
…
…
…
…
…
www.xilinx.com
From
12287
12543
16383
32767
3839
4095
4351
8191
8447
255
511
767
…
…
…
…
…
Memory Location
Table
4-10. These attributes are hex-
Block RAM Attributes
12032
12288
16128
32512
3584
3840
4096
7936
8192
256
512
To
…
…
…
…
…
0
129
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