XC5VLX110T-3FFG1136C Xilinx Inc, XC5VLX110T-3FFG1136C Datasheet - Page 195
![IC FPGA VIRTEX-5 110K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-3FFG1136C
Manufacturer Part Number
XC5VLX110T-3FFG1136C
Description
IC FPGA VIRTEX-5 110K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-3FFG1136C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-3FFG1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Multiplexers
delay to access the LUT. This operation is asynchronous and independent of the clock and
clock-enable signals.
Static Read Operation
If the 5-bit address is fixed, the Q output always uses the same bit position. This mode
implements any shift-register length from 1 to 32 bits in one LUT. The shift register length
is (N+1), where N is the input address (0 – 31).
The Q output changes synchronously with each shift operation. The previous bit is shifted
to the next position and appears on the Q output.
Shift Register Summary
•
•
•
•
•
•
Function generators and associated multiplexers in Virtex-5 FPGAs can implement the
following:
•
•
•
These wide input multiplexers are implemented in one level or logic (or LUT) using the
dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow LUT
combinations of up to four LUTs in a slice.
A shift operation requires one clock edge.
Dynamic-length read operations are asynchronous (Q output).
Static-length read operations are synchronous (Q output).
The data input has a setup-to-clock timing specification.
In a cascadable configuration, the Q31 output always contains the last bit value.
The Q31 output changes synchronously after each shift operation.
4:1 multiplexers using one LUT
8:1 multiplexers using two LUTs
16:1 multiplexers using four LUTs
www.xilinx.com
CLB Overview
195
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